ADI-Overview of the new ANSI/ESDA/JEDEC JS-002 CDM test standard

Component Charge Mode (CDM) ESD is considered to be the primary actual ESD model representing ESD charging and rapid discharge, which can appropriately represent what happens to the automatic processing equipment used in today's integrated circuit (IC) manufacturing and assembly. So far, in the process of device processing in the manufacturing environment, the major cause of ESD damage to ICs is from charging device incidents, which has been widely known. 1

Charging device model roadmap

The increasing demand for higher-speed IOs in ICs and the need to integrate more functions in a single package are driving the package size to increase. Therefore, maintaining the recommended target CDM level discussed in JEP1572, 3 will be a challenge. It should also be noted that although technology expansion may not have a direct impact on the target level (at least as low as 14 nm), these technologies improve transistor performance, which in turn can also support higher IO performance (transfer rate), so for IO designers , Achieving the current target level has also become difficult. Due to the inconsistency of the charging resistances of different testers, the published ESD Association (ESDA) roadmap recommended by 20204 that the CDM target level will need to be lowered again, as shown in Figure 1.

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Figure 1. Sensitivity limit prediction of charging device model in 2010 and later (Copyright 2016 EOS/ESD Association)

A quick glance at Figure 1 will not find a significant change in the CDM target level, but a further review of the data provided by ESDA (as shown in Figure 2) shows that the distribution of CDM ESD target levels is expected to have significant changes.

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Figure 2. Sensitivity distribution group prospect of charging device model (Copyright 2016 EOS/ESD Association)

Why is it important to discuss this change? It points out that a consistent method is needed to test the CDM of the entire electronics industry, and some inconsistencies caused by multiple test standards should be eliminated. It is now more important than ever to ensure that the manufacturing industry is properly prepared for the CDM roadmap discussed by ESDA. A key aspect of this preparation is to ensure that the data on the CDM robustness level of the device received by the manufacturing industry from various semiconductor manufacturers is consistent. The demand for a harmonized CDM standard has never been so strong. Coupled with continuous technological progress, IO performance will also be improved. This need for higher IO performance (and the need to reduce pin capacitance) forces IC designers to have no choice but to lower the target level, which in turn requires more precise measurements (in ANSI/ESDA/JEDEC JS-002) There are instructions).

New Joint Standard

There are four existing standards before ANSI/ESDA/JEDEC JS-002: traditional JEDEC (JESD22-C101)5, ESDA S5.3.16, AEC Q100-0117 and EIAJ ED-4701/300-2 standards8. ANSI/ESDA/JEDEC JS-002 (Charging Device Model, Device Level) 9 represents a major effort to unify these four existing standards into a single standard. Although all these standards produce valuable information, the existence of multiple standards is not a good thing for the industry. Different methods often produce different passing levels, the existence of multiple standards requires manufacturers to support different test methods, and meaningful information has not increased. Therefore, the following two points are very important: the single measurement level of IC charging device suppression capability is widely known to ensure that the CDM ESD design strategy is implemented correctly; the IC charging device suppression capability is the same as the ESD control level in the manufacturing environment it will be exposed to Unanimous.

In order to solve this problem, the ESDA and JEDEC CDM Joint Working Group (JWG) established in 2009 developed JS-002. In addition, JWG hopes to make technical improvements to FICDM based on the lessons learned since the introduction of Field Induction CDM (FICDM)10. , JWG hopes to minimize the impact on the electronics industry. In order to reduce the impact of the industry, the working group decided that the joint standard should not require the purchase of a new field induction CDM tester, and the pass/fail level should be as consistent as possible with the JEDEC CDM standard. The JEDEC standard is a widely used CDM standard, so JS-002 is consistent with the current manufacturing industry’s understanding of CDM.

Although the test methods of JEDEC and ESDA are very similar, there are some differences between the two standards that need to be resolved. JS-002 also tries to solve some technical problems. Some important issues are listed below.

Difference between standards

Field plate dielectric thickness

Verification module used to verify the system

Oscilloscope bandwidth requirements

Waveform verification parameters

Standard technical issues

The measurement bandwidth requirement is too slow for CDM

artificially make the pulse width in the JEDEC standard very wide

In order to achieve the goal and achieve unification, the following hardware and measurement choices were made. During the five-year documentation process, the working group made a lot of measurements before making these decisions.

Hardware selection

Use JEDEC dielectric thickness

Use JEDEC "coins" for waveform verification

It is forbidden to use ferrite in the discharge path

Measurement selection

System verification/acceptance requires an oscilloscope with 6 GHz bandwidth

Routine system verification allows the use of a 1 GHz oscilloscope

Minimize data corruption and discuss hidden voltage adjustment

Make the target peak current consistent with the existing JEDEC standard

Specify test conditions that match the JEDEC pressure level; for JS-002 test results, refer to test conditions (TC); for JEDEC and AEC, refer to volts (V)

For JS-002, adjust the field plate voltage to provide the correct peak current corresponding to the traditional JEDEC peak current requirement

Ensure that the larger package is fully charged

In order to ensure that the larger package is fully charged, a new procedure has been introduced

These improvements are explained below.

JS-002 hardware selection

JS-002 CDM hardware platform represents the combination of ESDA S5.3.1 probe assembly or test head discharge probe with JEDEC JESD22-C101 verification module and field board dielectric. Figure 3 shows the hardware comparison. There is no specific ferrite in the discharge path of the ESDA probe assembly. FICDM tester manufacturers believe that ferrite is necessary. Adding ferrite can increase the full width at half maximum (FWHH) rating of 500 ps and reduce Ip2 (second wave peak) to less than 50% of peak Ip1. So as to meet the traditional JEDEC requirements. JS-002 removes this ferrite, thereby eliminating this limiting factor in the discharge, making the discharge waveform more accurate, and the ringing phenomenon seen by the high-bandwidth oscilloscope at Ip1 no longer exists.

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Figure 3. Hardware schematic diagram of JEDEC and JS-002 platform

Figure 4 shows the difference between ESDA and JEDEC CDM standard verification modules. The ESDA standard provides two dielectric thickness options, combined with a verification module (the second option is an additional layer of 130 μm plastic film between the module and the field plate for testing devices with metal encapsulation covers). JEDEC verification module/FR4 dielectric represents a single small/large verification module and dielectric option, and there are many more JEDEC standard users supporting it.

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Figure 4. Comparison of ESDA and JEDEC verification modules JS-002 uses JEDEC module.

JS-002 measurement selection

In the data collection phase of the JS-002 standard, CDM JWG found that a higher bandwidth oscilloscope was needed to measure CDM waveforms. The 1 GHz bandwidth oscilloscope failed to capture the true peak value. Figures 5 and 6 illustrate this point.

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Figure 5. CDM waveforms of the large JEDEC verification module at 500 V JEDEC and JS-002 TC500 at 1 GHz

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Figure 6. CDM waveforms of the large JEDEC verification module at 500 V JEDEC and JS-002 TC500 at 6 GHz

Routine waveform inspections, such as daily or weekly inspections, can still be performed with a 1 GHz bandwidth oscilloscope. However, analysis of test sites in different laboratories shows that high-bandwidth oscilloscopes can provide better inter-site correlation. 11 Routine inspections and quarterly inspections are recommended to use a high-bandwidth oscilloscope. Annual verification or verification after replacement/repair of the tester hardware requires a high-bandwidth oscilloscope.

Table 1. JS-002 waveform data record example, showing the factors that cause TC (test condition) voltage 9

Tester—System #1

Polarity = positive

Oscilloscope bandwidth = 8 GHz

factor/offset final setting = 0.82

Module size

date

%RH

  Test Conditions

Software voltage

IP AVG (A)

T R AVG

TD AVG

IP2 AVG

IP2 (% IP1)

  Big

Day/Month/Year

X%

TC 500

500

12.1

275

610

4.3

36%

  small

Day/Month/Year

X%

TC 500

500

7.30

185

400

3.7

51%

  Big

Day/Month/Year

X%

TC 125

125

2.90

283

611

1.1

38%

  small

Day/Month/Year

X%

TC 125

125

1.90

201

395

1.1

58%

  Big

Day/Month/Year

X%

TC 250

250

6.00

276

609

2.2

37%

  small

Day/Month/Year

X%

TC 250

250

3.70

186

397

2.1

57%

  Big

Day/Month/Year

X%

TC 750

750

18.30

274

611

7.2

39%

  small

Day/Month/Year

X%

TC 750

750

11.0

190

398

6.1

55%

  Big

Day/Month/Year

X%

TC 1000

1000

24.40

276

612

9.2

38%

  small

Day/Month/Year

X%

TC 1000

1000

14.60

187

399

7.4

51%

Tester CDM voltage setting

CDM JWG also found that for different tester platforms, in order to obtain standard test waveforms that comply with the previous ESDA and JEDEC standards, the actual board voltage settings need to be quite different (for example, the specific voltage is set to 100 V or greater). This is not stated in any standard. The JS-002 ground determines the offset or factor required to scale the peak current (and the voltage represented by the test condition) to the JEDEC peak current level. JS-002 Appendix G has a detailed description of this. Table 1 shows an example of verification data that includes this feature.

Ensure that the oversized device is fully charged under the set test conditions

In the data collection stage of JS-002 development, a tester-related problem was also found: some test systems did not fully charge the large verification module or device to the set voltage before discharging. The large-value field plate charging resistance (the series resistance between the charging power supply and the field plate) of different test systems is inconsistent, which affects the delay time required for the field plate voltage to fully charge. As a result, the peak discharge current of different testers may be different, which affects the pass/fail classification of CDM, especially for large devices.

Therefore, the working group wrote a detailed Appendix H ("Determine the appropriate charge delay time to ensure that the large module or device is fully charged"), which describes the procedure for determining the delay time required for the device to be fully charged. When the peak current saturation point appears (Ip remains basically stable, setting a longer delay time will not change it), it means that the appropriate charging delay time has been reached, as shown in Figure 7. Determine this delay time to ensure that the ultra-large device can be fully charged to the set test conditions before discharging.

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Figure 7. An example of the relationship between peak current and charging time delay, showing the saturation point/charge time delay 9

Electronics industry gradually adopts JS-002

For companies that adopt the ESDA S5.3.1 CDM standard, the JS-002 standard replaces S5.3.1, and S5.3.1 should be discarded. For companies that previously used JESD22-C101, the JEDEC reliability test specification document JESD47 (prescribes all reliability test methods for JEDEC electronic components) has recently been updated, requiring JS-002 to replace JESD22-C101 (at the end of 2016). The transition period for JEDEC member companies to switch to JS-002 has now begun. Many companies (including ADI and Intel) have tested all new products using the JS-002 standard.

The International Electrotechnical Commission (IEC) recently approved and updated its CDM test standard IS 60749-2812. This standard is fully incorporated into JS-002 as its designated test standard.

The Automotive Electronics Council (AEC) currently has a CDM subcommittee, which is updating the Q100-011 (integrated circuit) and Q101-005 (passive components) CDM standard documents for automotive devices to include JS-002 and incorporate the requirements of AEC Test conditions of use. These tasks are expected to be completed and approved by the end of 2017.

Conclusion

Observing the CDM ESD roadmap provided by ESDA, we can see that under the drive of higher IO performance, CD
The M target level will continue to decrease. The manufacturing industry’s awareness of the device-level CDM ESD withstand voltage is more important than ever, and the CDM results of inconsistent products from different CDM ESD standards cannot convey this message. ANSI/ESDA/JEDEC JS-002 has the opportunity to become a true CDM test standard applicable to the whole industry. Eliminating the capacitance in the discharge path of the CDM test head can significantly improve the quality of the discharge waveform. Introducing a high-bandwidth oscilloscope for verification, raising the level of waveform verification to five test conditions, and ensuring proper charging delay time-all these measures have significantly reduced the difference in test results between different laboratories and improved the repeatability between sites. This is essential to ensure consistent data is provided to the manufacturing industry. After the electronics industry accepts the JS-002 standard, it will be able to better respond to the ESD control challenges ahead.