Common relational operators (reduction operators)

Written in front

The reduction operator is a monocular operator and also has an AND or NOT operation. The NOR rule is similar to the NOR rule of the bit operator, but the operation process is different. A bit operation is an AND-OR operation on the corresponding bits of the operand. If the operand is a few digits, the operation result is also a few digits. The reduction operation is different. The reduction operation is an AND or non-recursive operation on a single operand, and the final operation result is a one-bit binary number. The specific calculation process of the reduction operation is as follows: the first step first performs an AND-OR operation with the first and second bits of the operand, the second step performs an AND-OR operation with the third bit, and so on. Until the last bit. E.g:

reg [3: 0] B;

reg C;

C = & B;

Equivalent to

C = ((B [0] & B [1]) & B [2]) & B [3];

Engineering example

Below, Brother Dreamwing writes an example for everyone to verify whether the calculation result is as we said through simulation waveforms. The synthesizable module code is as follows

    / ************************************************* ***
     * Engineer: Brother Dreamwing
    * QQ: 761664056
     * The module function: Reduced statement operation module
    ********************************************** *** /
01 module reduce (clk, rst_n, c);
 02 input clk; // system clock input
03 input rst_n; // system reset
04
 05 output reg c; // Output register definition
06
 07 reg [3: 0] B; // Internal register definition
08
 09 always @ (posedge clk or negedge rst_n)
 10 begin
 11 IF (! Rst_n)
 12 begin
 13 c <= 0;
 14 B <= 4'b1111;
 15 end
 16 else
 17 begin
 18 c <= & B;
 19 end
 20 end
 twenty one
 22 endmodule
 

Write test code as follows

    / ************************************************* ***
     * Engineer: Brother Dreamwing
    * QQ: 761664056
     * The module function: Reduced statement test module
    ********************************************** *** /
01 `timescale 1ns / 1ps
 02 module tb;
 03 reg clk;
 04 reg rst_n;
 05
 06 wire c;
 07
 08 initial
 09 begin
 10 clk = 0;
 11 rst_n = 0;
 12 # 1000.1 rst_n = 1;
 13 end
 14
 15 always # 10 clk = ~ clk;
 16
 17 reduce reduce (
 18 .clk (clk),
 19 .rst_n (rst_n),
 20 .c (c)
 twenty one    );
 22 endmodule
 

View the simulation waveform as follows: 
       

It can be seen from the waveform that when all four bits of the variable B are high, the variable C that is finally output is high because it is a "logical AND" operation.

So what happens if we add a zero to the variable B? We simulate as follows: 
       

It can be seen that if there is zero in the variable B, the output result will be low due to the "logical AND".