The working principle and application of DSD-1700 converter adopting DSD coding method

1 Introduction

The digital audio equipment of the new century has entered the market, and the SACD introduced by Sony adopts the new DSD (DirectStreamDigital) encoding method. This simple coding method can realize high-precision D/A transform coding. DSD-1700 is the first IC chip that can complete direct data stream conversion. It is easy to operate and can also be used as an analog FIR filter.

In the DSD mode, the analog signal of the source is subjected to a delta sigma modulation signal at a frequency of 64 fs, and the analog signal can be directly obtained by filtering the low-pass filter.

But in actual DSD/A conversion, SACD has certain requirements on the function and characteristics of the low-pass filter. The active filter formed by the op amp in the general CD player cannot meet this requirement. 1bit digital data has a lot of information on the time axis. To restore an analog signal from it, a low-pass filter that conforms to the △Σ modulation frequency characteristic must be used. Specifically, it needs to be realized with an analog FIR filter. The basic action of DSD-1700 is an analog FIR filter.

The working principle and application of DSD-1700 converter adopting DSD coding method

2DSD-1700 working principle

The workpiece principle diagram of DSD-1700 is shown in Figure 1. It is composed of DSD signal interface part, working pulse generator, shift register and analog FIR filter. In order to minimize the error caused by the time axis and the influence of power supply voltage and noise, the overall structure of DSD-1700 adopts the form of double differential circuit.



2.1DSD input/timing generator

Figure 2 shows the timing relationship of DSD-1700 input signals. SCK (256fo) is the system clock for internal working timing. DCK (64fs) is a DSD data clock that reads 64fs frequency. The DSD data of 1bit64fs is input from DATA. After the timing generator processes the internal working time relationship of the clocks such as 256fs and 64fs, the timing signal is generated in the later stage.

2.2 Working pulse generator/shift register

The DSD signal of 64fs is sent to the shift register through the working pulse generator. The working pulse generator is used to generate the clock of the DSD signal. This kind of clock can minimize the influence of the timing conversion error and noise of the clock. The shift register converts the DSD signal into an 8-bit input data block required for analog FIR filtering.



2.3 Analog FIR filter

The basic circuit of an analog FIR filter is shown in Figure 3. The input DSD signals are added together after being delayed and converted into analog signals. Figure 4 is the equivalent circuit of the 8-bit analog FIR filter actually used by the DSD-1700. It consists of 8 buffer amplifiers and a resistor network, and the resistance value of the resistor network determines the filter coefficient.



In DSD-1700, this 8-level analog FIR filter has four output terminals: hot end (HOT) plus and minus and cold end (COLD) plus and minus four output terminals, operating in a double differential circuit. Finally, it is converted into an analog output by an external double differential single-ended conversion circuit.

Specifications of 3DSD-1700

DSD-1700 adopts 28-pin SSOP package. Table 1 shows the function description of each pin. Its main electrical characteristics are listed in Table 2. Since the re-interpolation frequency bandwidth of the DSD method is as high as 110kHz, the test standards for the main audio characteristics such as THD+N and dynamic range are not yet clear. Therefore, the electrical parameters of DSD-1700 are determined based on the conditions of the CD test.


4DSD-1700 application circuit

Figure 5 is the basic connection circuit of DSD-1700. The circuit connection is very simple. In addition to the input components, there are 9 capacitors for current filtering. Since the self-locking circuit of the internal analog FIR filter requires independent power and ground wires, DSD-1700 has multiple pairs of power inputs. C1～C9 are the capacitors for power decoupling, and 0.1μF ceramic capacitors and 0.1μF ceramic capacitors can be selected respectively. 100μF high-quality electrolytic capacitors are connected in parallel. In addition, the power trace on the printed board also needs to be considered.


Figure 6 is the actual conversion circuit that converts the received DSD-1700 output double-difference signal into a single-ended analog output. The circuit is composed of three operational amplifiers. IC1 and IC2 constitute a differential current/voltage conversion circuit, and IC3 and 0dB differential amplifier. Due to the large bandwidth of the signal processed by DSD, great attention should be paid to the gain bandwidth product and dynamic characteristics of the operational amplifier.

If DSD-1700 is used to make SACD players, analog LPF must be added in the latter stage to control the bandwidth and the rate of decrease of the transition zone. In addition, a piece of DSD-1700 can only process a single channel signal, so a general stereo player needs 2 pieces.

DSD-1700 has been used in Sony’s stereo equipment corresponding to various levels of DSD signals, and has received unanimous praise.