How to reduce the cost of silicon photonics product testing

Computing and data communications organizations have always wanted to discover results in data speed and computing power. Many in the industry believe that chip-to-chip and on-chip photonic technologies will become important technologies that will affect future computing. The silicon photoelectric technology competition is in full swing, and hardware manufacturers are eager to share this big cake of more than 2 billion US dollars. Although applications supporting on-chip lasers have existed for many years, the high costs associated with manufacturing, testing, and calibration have hindered the widespread adoption of silicon photonics applications.

This article will introduce and compare a variety of laser technologies used in the field of silicon optoelectronics, including cleavage surface, hybrid silicon laser and etching surface technology. We will also delve into the testing methods used for various technologies, and study how testing can play an important role in driving cost reduction and promoting the widespread popularization of silicon photonics technology.

Cleaved Facet Lasers

Figure 1 shows how to cut a semiconductor wafer based on indium phosphide (InP) into crystal strips to form a mirror for edge-emitting lasers. These crystal bars are stacked vertically one by one, and then a mirror coating is applied to the cleavage surface. During the cleavage process, a large number of crystal bars will be formed, and each laser on each crystal bar needs to be tested to determine its function. However, the wafer test requires these fragile semiconductor wafers to be operated by hand or machine, and one is generally tested. Therefore, this process is quite slow and expensive, and is limited to room temperature testing, so as not to take too long for the tester to test a crystal bar. The fragile crystal bar must be handled with care and gentleness during the test, otherwise the laser on the crystal bar is easily damaged.



Figure 1: The manufacturing steps of the cleavage surface and the etching surface laser show that they use different processes.

After passing the crystal bar test, the crystal bar is continuously cut into a single independent laser chip, and then calibrated with the silicon photonic chip in an active way. This process is also expensive because the laser chip must be powered up and moved during the calibration process until enough light is coupled into the silicon photonic waveguide. At this time, the position of the laser chip needs to be locked on the silicon photonic chip. Since the laser on the crystal bar has only been tested at room temperature, we still do not know whether the laser has acceptable performance at the extreme temperature within the working range. Because of this unknown condition, the silicon photonic chip attached (Cleaved Facet Lasers) must also be tested in the entire temperature range, which requires additional resources and adds more costs.

One possibility is to do a full temperature range crystal bar level test and produce a laser chip with a known good die (KGD), but this approach is not only very expensive, but also very slow, because the laser crystal bar has only a small number of devices. In addition, the crystal bar needs to be placed at two extreme temperatures, cold and hot during the test.

Hybrid silicon lasers

Hybrid silicon lasers, such as products developed and used by Intel for silicon photonics applications, use glass glue to fuse InP wafers and silicon wafers together instead of using the "flip chip" method in other laser technologies. The advantage of this method is that it does not require calibration, because the result of further processing after the InP is attached to the silicon substrate is a silicon laser. The disadvantage is that there is no way to test the InP wafer before it is integrated with the silicon base, so if the InP on a given silicon photonic chip is bad, the chip can only be discarded.

Because the InP wafer is fused to the silicon wafer, the actual InP area required by this method is generally larger, which is basically equal to the size of the silicon photonic chip. Cleavage and etching surface lasers have advantages in this regard, because only the laser cavity and its bonding pads require the use of expensive InP. However, if a certain developed process allows the placement of InP on silicon photonic wafers For small chips of wafers, the amount of InP used will be significantly reduced.

Etched facet lasers

As shown in Figure 1, Etching Surface Technology (EFT) allows crystal planes to be determined by high-precision photolithography rather than random mechanical cutting methods. Lithography allows the cavity size and the position of the surface to be determined within 0.1 μm. The result is unprecedented consistency and yield, and can build structures that cannot be built with traditional technology. After adopting the etching surface technology, the formed device surface has a particularly high precision, which can realize low-cost and passive calibration with silicon-based photons. The accuracy of active calibration can be achieved only at the cost of the automated process.

Because the laser can be completely formed under the condition that the wafer is intact (while the wafer must be cut during the formation of the cleavage surface laser), wafer-level laser testing can also be performed. Assuming there are thousands or tens of thousands of lasers on a 2-inch or 3-inch wafer, depending on the requirements of silicon photonics applications, testing the wafer to extreme temperatures during wafer-level testing will be extremely cost-effective.

Another advantage is that the etching surface laser can be fully manufactured and automated testing before being divided into individual chips. For example, using in-house custom test equipment for etched surface lasers, BinOptics can provide InP-based lasers for qualified silicon photonics applications. All lasers on the wafer are tested with automated, high-throughput test operations over the entire temperature range required for silicon photonics applications.

Figure 2 shows the working principle of an automated wafer-level test station for testing etched surface lasers. The figure shows a wafer workbench with an etched surface laser on it. There is a large lens at a position far away from the wafer table, which is used to capture the laser light emitted by the laser on the etching surface during the test on the wafer. During the test, the wafer table moves the wafer in the x-y plane to keep the position of the device under test and the lens unchanged. The probe arm brings the probe to the surface of the wafer to perform various tests on the laser.



Figure 2: The lens captures the light from the laser on the etched surface to be tested. Wafer probes perform photo-current-voltage tests on the laser still on the wafer.

Light-current-voltage (LIV) test is common to all laser types. The laser is first collected by the lens and then directed to the detector for light intensity measurement. For edge-emitting etched surface lasers, the general lens only collects part of the laser, so the actual optical power must be determined by calibration factors. Full-spectrum testing can be performed at different currents and temperatures to ensure that the device has the desired performance over the entire operating temperature range. In this, the laser light from the lens is directed to the spectrum analyzer. For low temperature conditions, a transparent chamber should be added to the test device, and the chamber should be filled with nitrogen to prevent condensation from forming on the wafer under low temperature conditions.

The future is here

There are many different ways to realize the huge potential of silicon photonics applications. They all have their own benefits and challenges, depending on the specific use. Only by trying to overcome cost, yield and performance barriers can we succeed in this emerging industry. The ability to provide lasers with known qualified chips will be an important factor for the company to stand out.