A Method for Improving Testability of Telemetry Signal Processor

Testability is defined as the design characteristics of a product that can determine its status in a timely and accurate manner, isolate its internal faults, and design for the purpose of improving product testability is called design for testability. Testability is a new discipline alongside reliability and maintainability. Its development and application are of great significance for improving product quality and reducing product life cycle costs. With the continuous advancement of integrated circuit design methods and process technology, the testability of integrated circuits has become an important factor in improving product reliability and yield. According to the design principle of the signal processor in the telemetry product, the test coverage of the signal processor is improved by increasing the BIT.

    1 Introduction to signal processor

    Hardware circuit software is the development trend of circuit design. With the help of large-scale integrated FPGA and efficient design software, not only can a variety of digital logic system functions be realized by directly designing the chip structure, but also due to the flexible pin definition, which reduces the work of signal processor circuit diagram design and circuit board design Volume and difficulty. This design based on programmable logic devices greatly reduces the number of chips, reduces the volume of the system, and improves the reliability of the system. At the same time, it also increases the test complexity of the signal processor and reduces the fault isolation rate.

    The signal processor mainly completes the functions of time-sharing collection of voltage analog signals, RS422 bus signal reception and encoding output. The functional block diagram is shown in Figure 1.



    Figure 1 Block diagram of signal processor

    2 Analysis of the current situation of signal processor testing

    The signal processor is an important component of the telemetry product, and its testability basically determines the testability of the telemetry product, so it is of great significance to improve the testability of the signal processor. It can be seen from Figure 1 that the signal processor needs to test more nodes, mainly including multiple analog signal conditioning circuits, switches, A/D converters, RS422 bus interface chips, PCM code output circuits, logic modules inside the FPGA, There are about 34 test nodes in total, such as secondary power supply.

    In the ground or laboratory environment, using signal simulators, multimeters, oscilloscopes, data receiving equipment, etc. to test the signal processor can assess all test nodes, and basically achieve 100% test coverage and fault isolation rate of the signal processor.

    Under the premise of normal power supply, secondary power conversion and PCM output, the working status of some modules can only be obtained through the PCM data received during the on-hook self-test, including the conditioning circuit, switch, and switch where the "power supply" signal is located. Some functions of A/D converter, analog quantity processing module and coding control module, the test coverage is about 24%. When any one or more of the 4 units fails, the further isolation of the fault cannot be completed through data analysis, thus forming a fuzzy group with a ambiguity of 4, and the fault isolation rate is 0%.

    3 BIT design analysis

    3.1 BIT analysis of a single analog signal acquisition channel

    By analyzing the circuit of the double-dotted line in Figure 1, the fault tree is established as shown in Figure 2, and the correlation graph model formed according to the fault tree is shown in Figure 3, and the first-order correlation and correlation D matrix are obtained as shown in Figure 4. Show.



    Figure 2 Fault tree



    Figure 3 Graphical model of correlation



    Figure 4 First-order correlation and correlation D matrix



    Figure 5 Diagnostic tree and fault dictionary

    Through the analysis of the D matrix, the redundant test points and fuzzy groups are identified, the test point selection for detection is completed, and the diagnosis tree and the fault dictionary are generated as shown in Figure 5.

    3.2 BIT design of a single analog signal acquisition channel

    Part of the circuit BIT analysis is based on identifying the fault and fault location by obtaining the state of the test point. According to the particularity of the signal processor, the design adopts the method of introducing stimulus signals for each test point of the circuit to realize the function of judging whether the functional module has a fault. The BIT scheme is shown in Figure 6.



    Figure 6 Analog signal BIT program

    Add a D/A converter circuit and a switch matrix module to the signal processor, and add a self-checking module to the FPGA; when the signal processor is powered on, the self-checking module controls the switch matrix to connect to each test point, and the D/A converter is connected Enter a specific voltage value; the status of each module can be understood by comparing the return value of the final test of the circuit with the imported value. Take the analog signal "power supply" test channel as an example to illustrate the BIT workflow.

    (1) The preset D/A output value of the self-checking module is 4 V. (2) The 4 V voltage is connected to the front end of the conditioning circuit where the "power supply" signal is located through the switch matrix. (3) The self-checking module compares the data obtained through the A/D converter with the predetermined value. (4) If the comparison results are consistent, the output "000" indicates that there is no fault, and the self-inspection ends. (5) If the comparison results are inconsistent, control the switch matrix to connect the 4 V voltage to the rear end of the conditioning circuit, that is, the front end of the switch, and the self-check module compares the data obtained through the A/D converter with the predetermined value. (6) If the comparison results are consistent, the output "110" indicates that the conditioning circuit is faulty, and the self-check is over. (7) If the comparison results are inconsistent, control the switch matrix to connect the 4 V voltage to the rear end of the switch, that is, the front end of the A/D converter, and the self-check module will compare the data obtained through the A/D converter with the predetermined value . (8) If the comparison results are consistent, the output "101" indicates that the exchange sub is faulty, and the self-check is over. (9) If the comparison results are inconsistent, "100" indicates that the A/D converter is faulty, and the self-check is over.

    There is a blind spot in this process, that is, the analog signal processing module is faulty. Because this failure may also cause the switch output and A/D converter output failure, a single process cannot be identified and isolated. After all analog channels are added to this process, the above-mentioned faults can be judged and isolated by the principle of majority.

    3.3 RS422 data channel BIT design

    RS422 data reception has only two-level functional modules, and fault determination and isolation are relatively simple. It only needs to increase the corresponding number of standard RS422 bus data streams in the FPGA, and access the RS422 bus interface chip input terminal or RS422 data processing module through the RS422 bus interface chip, the switch matrix and the bus selector. The RS422 data channel BIT scheme is shown in Figure 7.



    Figure 7 RS422 data channel BIT scheme

    After the signal processor is powered on, the self-checking module first sends out RS422 information in a predetermined format, and controls the switch matrix to cut into the input end of the RS422 interface circuit, and compare the received data with the original data. If they are consistent, there is no fault; otherwise, the predetermined data is cut into the back end of the RS422 interface circuit through the bus selector, and then the received data is compared with the predetermined data. If the comparison result is consistent, the RS422 interface circuit is faulty, otherwise RS422 data processing The module is faulty, but the RS422 interface circuit cannot be identified at the same time.

    3.4 The overall BIT design of the signal processor

    Through the BIT design of a single analog signal acquisition channel and RS422 data channel, the overall BIT design result of the final signal processor is shown in Figure 8.



    Figure 8 The design block diagram of the signal processor after perfecting the BIT

    The self-inspection module is designed for the entire BIT. The self-inspection module needs to control D/A conversion, switch matrix switching, bus selector working status, generate required excitation signals, complete data interpretation, and generate fault codes. The functional block diagram of the self-checking module is shown in Figure 9.



    Figure 9 Functional block diagram of the self-checking module

    4 Conclusion

    After the signal processor completes the BIT design, the test coverage in the on-hook self-test state is close to 100%. If only a single fault occurs in the signal processor, the fault isolation rate is as high as 100%; if multiple faults occur, the closer the fault occurs to the signal input front end, the higher the fault isolation rate, and vice versa, the lower the average fault isolation rate is about 70% . In short, after the signal processor increases the BIT, the test coverage and fault isolation rate in the on-hook self-test state are greatly improved.