Enhanced, depletion type MOS field effect transistor

According to the different conduction mode, MOSFET is divided into enhancement type and depletion type. The so-called enhanced type refers to: when VGS=0, the tube is in an off state, and after adding the correct VGS, the majority of carriers are attracted to the gate, thereby "enhancing" the carriers in this area and forming a conductive channel . The N-channel enhancement mode MOSFET is basically a symmetrical topological structure, which is to generate a layer of SiO2 thin film insulating layer on the P-type semiconductor, and then use the photolithography process to diffuse two highly doped N-type regions, from the N The type region leads to electrodes, one is the drain D and the other is the source S. A layer of metal aluminum is plated on the insulating layer between the source electrode and the drain electrode as the gate G.
When VGS=0 V, there are two back-to-back diodes between the drain and the source. Applying a voltage between D and S will not form a current between D and S.
When a voltage is applied to the gate, if 0<VGS<VGS(th), through the capacitive electric field formed between the gate and the substrate, the multiple holes in the P-type semiconductor near the gate are repelled downwards , There appears a thin depletion layer of negative ions; at the same time, the minority carriers will be attracted to move to the surface, but the number is limited, not enough to form a conductive channel to communicate between the drain and the source, so it is still not enough to form the drain current ID .
Further increase VGS, when VGS>VGS(th) (VGS(th) is called the turn-on voltage), since the gate voltage is already relatively strong at this time, more electrons are accumulated in the P-type semiconductor surface layer near the bottom of the gate , A channel can be formed to communicate the drain and source. If the drain-source voltage is applied at this time, the drain current ID can be formed. The electrons in the conductive channel formed under the gate are called the inversion layer because of the opposite polarity to the carrier holes of the P-type semiconductor. As VGS continues to increase, ID will continue to increase. ID=0 when VGS=0V, drain current will only appear after VGS>VGS(th), so this kind of MOS tube is called an enhanced MOS tube.
The control relationship between VGS and drain current can be described by the curve iD=f(VGS(th))|VDS=const, which is called the transfer characteristic curve, as shown in Figure 1.
The magnitude of the slope gm of the transfer characteristic curve reflects the control effect of the gate-source voltage on the drain current. The dimension of gm is mA/V, so gm is also called transconductance. Transconductance.


Figure 2-54 (a) is a schematic diagram of the structure of an N-channel enhancement mode MOSFET, and its circuit symbol is shown in Figure 2-54 (b). It uses a P-type silicon wafer with a lower doping concentration as the substrate, and uses a diffusion process to diffuse two high-doping concentration N-type regions (indicated by N+) on the substrate, and lead to this N-type region The two ohmic contact electrodes are called the source (represented by S) and the drain (represented by D). The surface of the substrate between the source region and the drain region is covered with an insulating layer of silicon dioxide (SiO2). A metal aluminum layer is deposited on this insulating layer and an electrode is drawn as a gate (indicated by G). An ohmic contact electrode drawn from the substrate is called the substrate electrode (denoted by B). Since the grid and other electrodes are insulated from each other, it is called an insulated grid field effect transistor. In Figure 2-54 (a), L is the channel length and W is the channel width.


The MOSFET shown in Figure 2-54, when no voltage is applied between the gate G and the source S, that is, UGS=0
At this time, because the gap between the drain and source N+ type regions is a P-type substrate, it is equivalent to two back-to-back PN junctions. The resistance between them is as high as 1012W, which means that there is no difference between D and S. With a conductive channel, no matter what polarity voltage is applied between the drain and source, the drain current ID will not be generated.
When the substrate B and the source S are short-circuited, and a positive voltage is applied between the gate G and the source S, that is, UGS﹥0, as shown in Figure 2-55 (a), then the gate and the substrate An electric field directed from the gate to the substrate is generated between. Under the action of this electric field, the holes near the surface of the P substrate are repelled and move downwards. The electrons are attracted by the electric field and move towards the surface of the substrate, recombine with the holes on the surface of the substrate to form a depletion layer. If the UGS voltage is further increased to make UGS reach a certain voltage UT, all the holes in the surface layer of the P substrate are repelled and depleted, and a large number of free electrons are attracted to the surface layer, changing from quantitative to qualitative change, making the surface layer become The N-type layer with multiple free electrons is called the "inversion layer", as shown in Figure 2-55(b). The inversion layer connects the two N+-type regions of the drain D and the source S to form an N-type conductive channel between the drain and the source. The UGS value required to start the formation of the conductive channel is called the threshold voltage or turn-on voltage, which is represented by UT. Obviously, there is a channel only when UGS>UT, and the larger the UGS, the thicker the channel, the smaller the on-resistance of the channel, and the stronger the conductivity. This is why it is called enhanced.
Under the condition of UGS﹥UT, if a positive voltage UDS is applied between the drain D and the source S, current will flow in the conductive channel. The drain current flows from the drain region to the source region. Because the channel has a certain resistance, a voltage drop is generated along the channel, so that the potential of each point of the channel gradually decreases from the drain region to the source region along the channel, and is close to the drain region. The voltage UGD at one end has a value of UGD=UGS-UDS, and the corresponding channel is thin; the voltage at one end close to the source region is equal to UGS, and the corresponding channel is thick. In this way, the channel thickness is no longer uniform, and the entire channel is inclined. As the UDS increases, the trench near one end of the drain region becomes thinner and thinner.

When UDS increases to a certain critical value so that UGD≤UT, the drain channel disappears, leaving only the depletion layer. This situation is called channel "pre-pinch off", as shown in Figure 2-56 (a ) As shown. Continue to increase UDS (ie UDS>UGS-UT), and the pinch point moves toward the source, as shown in Figure 2-56 (b). Although the pinch-off point is moving, the voltage drop in the channel region (source S to the pinch-off point) remains unchanged, which is still equal to UGS-UT. Therefore, the excess voltage of UDS [UDS-(UGS-UT)] is all reduced to the pinch-off area, and a strong electric field is formed in the pinch-off area. At this time, electrons flow from the source to the pinch-off region along the channel. When the electrons reach the edge of the pinch-off region, they will quickly drift to the drain under the action of the strong electric field in the pinch-off region.
depletion type. The depletion type means that a channel is formed when VGS=0, and when the correct VGS is added, the majority of carriers can flow out of the channel, thus "depleting" the carriers and turning the tube off.
Depletion-mode MOS field effect transistors are pre-doped with a large number of positive ions in the SiO2 insulating layer during the manufacturing process. Therefore, when UGS=0, the electric field generated by these positive ions can also be in the P-type substrate. Enough electrons are induced to form an N-type conductive channel.
When UDS>0, a larger drain current ID will be generated. If UGS<0, it will weaken the electric field formed by positive ions, narrow the N channel, and reduce the ID. When UGS is more negative, the channel disappears when it reaches a certain value, ID=0. UGS with ID=0 is also called pinch-off voltage, which is still expressed by UP. UGS<UP channel disappears, which is called depletion type.
The structure of the N-channel depletion MOSFET is similar to that of the enhancement MOSFET, except that the channel already exists when the gate voltage uGS=0 of the N-channel depletion MOSFET. The N channel is fabricated between D and S on the surface of the substrate in advance by ion implantation, which is called the initial channel. The structure and symbol of the N-channel depletion MOSFET is shown in Figure 1. (a), which is doped with a large amount of metal positive ions in the SiO2 insulating layer under the gate. So when VGS=0, these positive ions have induced an inversion layer and formed a channel. Therefore, as long as there is a drain-source voltage, there is a drain current. When VGS>0, the ID will be further increased. When VGS<0, the drain current gradually decreases as VGS decreases, until ID=0. The VGS corresponding to ID=0 is called the pinch-off voltage, which is represented by the symbol VGS(off), and sometimes also represented by VP. The transfer characteristic curve of N-channel depletion MOSFET is shown in Figure 1.(b).


(A) Structure diagram 　　　　　　(b) Transfer characteristic curve
Figure 1. Structure and transfer characteristic curve of N-channel depletion MOSFET
Because the depletion MOSFET has a channel between the drain and the source when uGS=0, so long as uDS is added, there will be iD flow. If the positive gate voltage uGS is increased, the electric field between the gate and the substrate will induce more electrons in the channel, the channel becomes thicker, and the conductance of the channel increases.
If a negative voltage (ie uGS<0=) is applied to the gate, positive charges will be induced on the corresponding substrate surface. These positive charges cancel the electrons in the N-channel, thereby generating a depletion layer on the substrate surface, making The channel narrows and the channel conductance decreases. When the negative gate voltage increases to a certain voltage Up, the depletion region extends to the entire channel, and the channel is completely pinched off (depleted), even if uDS still exists , There will be no drain current, that is, iD=0. UP is called pinch-off voltage or threshold voltage, and its value is usually between -1V-10V. The output characteristic curve and transfer characteristic curve of N-channel depletion MOSFET are respectively As shown in Figure 2-60 (a) and (b).
In the variable resistance area, the relationship between iD and uDS and uGS is still


In the constant current region, the relationship between iD and uGS still satisfies the formula (2-81), namely


If the influence of uDS is considered, iD can be approximated as


For depletion-type FETs, the formula (2-84) can also be expressed as


In the formula, IDSS is called the saturation leakage current when uGS=0, and its value is


The working principle of P-channel MOSFET is exactly the same as that of N-channel MOSFET, except that the conductive carriers are different and the polarity of the power supply voltage is different. This is the same as the bipolar transistor has NPN type and PNP type.