Schematic and circuit diagram of the inverting adder

1. What is an adder
The adder is to implement addition.
is a device that produces the sum of numbers. The addend and the addend are inputs, and the device where the sum and carry are outputs is a half adder. If the addend, addend, and low-order carry are input, and the sum and carry are output, it is a full adder. It is often used as a computer arithmetic logic component to perform logical operations, shifts and instruction calls.



For 1-bit binary addition, there are five related quantities: 1, the addend A, 2, the addend B, 3, the carry CIN of the previous bit, 4, the sum of the two-digit addition S, 5. The carry COUT generated by the addition of the two digits. The first three quantities are input quantities, the last two quantities are output quantities, and the five quantities are all 1 digits.
For 32-bit binary addition, there are also five related quantities: 1, the addend A (32 bits), 2, the addend B (32 bits), 3, the carry CIN of the previous bit (1 bit)


4. The sum S (32 bits) of this two-digit addition, 5, the carry COUT (1 bit) generated by this two-digit addition.
To achieve 32-bit binary addition, a natural idea is to repeat the 1-bit binary addition 32 times (ie, bitwise carry adder). This is undoubtedly feasible and easy to do, but since each CIN is provided by the previous COUT, the second digit must be calculated after the first digit before the calculation can begin; the third digit must be After the result is calculated in the second digit, the calculation can be started, and so on. The 32nd bit must be calculated in the first 31 bits before the calculation can be started. In this way, the time required to implement 32-bit binary addition is 32 times the time required to implement 1-bit binary addition.
  basic method
It can be seen that the above method is to carry out the 32-bit addition 1-bit 1-bit serially. To shorten the time, we should try to parallelize the above-mentioned process.
  Types of



In terms of unit element adders, there are two basic types: half adders and full adders.
The 　　 half adder has two inputs and two outputs. The input can be identified as A, B or X, Y, and the output is usually identified as combined S and hexadecimal C. A and B become S after XOR operation, and become C after AND operation.
The full adder introduces the input of hexadecimal values to calculate larger numbers. In order to distinguish the two base lines of the full adder, the input terminal is marked as Ci or Cin, and the output terminal is marked as Co or Cout. Half adder is abbreviated as H.A., full adder is abbreviated as F.A..
Half adder: The circuit diagram of the half adder. The half adder has two binary inputs. It adds the input values and outputs the result to the sum (Sum) and base (Carry). Although the half adder can generate hexadecimal values, the half adder itself cannot handle hexadecimal values.
Full adder: The full adder has three binary inputs, one of which is the input of the hexadecimal value, so the full adder can handle the hexadecimal value. The full adder can be combined with two half adders.
Note that the last OR gate of the hexadecimal output terminal can also be replaced by the XOR gate, and there is no need to change the rest. Because the difference between OR gate and XOR gate is only when the inputs are both 1, and this possibility no longer exists.
2. The principle of the adder
Suppose that the i-th input of an n-bit adder is ai, bi, ci, and the output si and ci+1, where ci is the carry from the low order, ci+1 (i=n-1, n-2,..., 1, 0) is the carry to the higher order, c0 is the carry input of the entire adder, and cn is the carry output of the entire adder. Then and



Si=aiii+ibii+iici+aibici, (1) carry ci+1=aibi+aici+bici, (2)
令 gi=aibi, (3)
Pi=ai+bi, (4)
then ci+1= gi+pici, (5)
As long as aibi=1, a carry to the i+1 bit will be generated, and g is the carry generation function; similarly, as long as ai+bi=1, ci will be transferred to the i+1 bit, so p is called the carry transfer function . Expanding the formula (5), we get: ci+1= gi+ pigi-1+pipi-1gi-2+...+ pipi-1...p1g0+ pipi-1...p0c0(6).
As the number of bits increases, the formula (6) will lengthen, but the depth of three logic levels is always maintained, so the delay in forming the carry is a constant independent of the number of bits. Once the carry (c1~cn-1) is calculated, the sum can also be obtained by equation (1).
The adder that uses the above formula to generate all carry bits in parallel is a look-ahead adder. Generating gi and pi requires gate delay, ci requires two stages, si requires two stages, and a total of five stages of gate delay are required. Compared with the series adder (generally 2n gate delay), (especially when n is relatively large) the delay time of the advance bit adder is greatly shortened.
3. Equivalent schematic diagram of inverting adder
Inverting adder circuit, also known as inverting summing circuit, means that more than one input signal enters the inverting input terminal, and the output result is the addition of multiple signals (the voltage polarity is opposite). In the circuit a in the figure, when R1=R2=R3=R4, its output voltage=IN1+IN2+IN3, which constitutes an inverting adder circuit. When R4>R1, the circuit also has a signal amplification function.



Diagram Inverting adder and principle equivalent diagram
The basic circuit structure of the 　　 inverting adder is an inverting amplifier. It can be seen from its "virtual ground" characteristic that both input terminals have 0V ground potential. This determines the control purpose of the circuit, which is to make the potential of the inverting input terminal 0V (the target value of the non-inverting input terminal is 0V). The circuit parameters and input signal values of the circuit in the above figure a are analyzed as examples, and the equivalent diagram shown in the figure b above can be obtained. The bias circuit of the inverting adder is still in the form of a series voltage divider as a whole, but the input loop involves the circuit principle of resistor shunting in parallel. The equation can be listed: IR4=IR1+IR2+IR3. The "secret" of the inverting adder is thus revealed.
Since the inverting input terminal is ground potential 0V, when the input signal IN3=0V, no signal current is generated in this branch, which is equivalent to no signal input, which becomes IN1+IN2=-OUT. When IR1(1V/10k)=0.1mA, IR2(1V/10k)=0.1mA, then only when OUT output is -2V, the condition of IR4=IR1+IR2 is satisfied.
If the principle equivalent diagram is further simplified (circuit c in the figure), a very familiar figure will come into our minds: Isn’t this just an inverting amplifier circuit? Yes, that’s right, inverted summation The (inverting adder) circuit is an inverting (including amplification and attenuation) device.
In practical applications, due to the obvious defects of the non-inverting adder, and the extremely high input impedance, the signal input current can only form a self-loop through multiple IN terminals (it will cause the input signal voltage to be involved in each other and change, resulting in larger calculation errors) , Unless the internal resistance of various IN signal sources is very small, it will not affect the calculation accuracy. Therefore, there are fewer applications. Due to its "virtual ground" characteristics, the input impedance of the inverting summation circuit is extremely low, so that the input current of each signal enters the input terminal in "convergence mode", which will not cause the current to flow between the input signals, so it can ensure the accuracy of calculation , More applications.
Four, inverting adder circuit and principle (picture)