Design analysis of high measurement of weak analog signal

If a scale with a measuring range of 10 kilograms can distinguish a weight change of 1 gram, then the main component of the scale is often an incremental accumulation analog-to-digital converter. When the designer needs the temperature measurement to reach 0.01 degrees, the incremental accumulation ADC is often the solution. Incremental accumulation ADCs can also replace those traditional successive approximation register ADCs with a gain stage added in front. Because these data converters are very suitable for measuring small changes in the real world, precision instruments such as temperature sensors, balances, transducers, flow meters, and countless other types of sensors are very suitable for incremental accumulation ADCs.
Incremental accumulation ADC may seem complicated on the surface, but in fact it is a data converter composed of a series of simple components. The incremental accumulation ADC is composed of two main components: an incremental accumulation modulator that performs analog-to-digital conversion and a digital low-pass filter/decimation circuit. The basic building blocks of the incremental accumulating modulator (integrated operational amplifier, summing node, comparator/1-bit ADC and 1-bit DAC) are shown in Figure 1. The charge balance circuit of the modulator forces the digital output bit stream of the comparator to represent the average analog input signal. While returning the output of the comparator to the 1-bit DAC of the modulator, it is also processed by a low-pass digital filter. This filter mainly calculates the number of 0s and 1s, and removes a lot of noise, thereby realizing up to 24-bit data converters.




Figure 1: Incremental accumulation ADC consists of an incremental accumulation modulator that performs analog-to-digital conversion, followed by a digital filter and decimator
Analog: analog
Integrator: integrator
comparator: comparator
1-bit ADC: 1-bit ADC
Digital filter: digital filter
Decimator: extractor
Digital output: digital output
1-bit DAC: 1 bit DAC
1-bit data stream: 1-bit data stream
Delta sigma modulator: incremental accumulative modulator
A major obstacle to achieving more bit resolution is noise. For designers who are trying to distinguish microvolt (μV) level changes from thermocouples, sensors, or other low-level signal sources, noise will be a major problem. The noise floor consists of the sum of all unwanted external and noise sources around the modulator. And the thicker the noise floor, the harder it is to detect real changes in the analog input signal you are trying to test.
Oversampling, noise shaping, digital filtering and decimation are four important methods used by incremental accumulation converters to reduce noise and generate high-resolution output data. Assuming that the input signal of a data converter is sampled at the frequency fS, according to the Nyquist theorem of the data, fS must be at least twice the input frequency (fIN=fS/2). Oversampling is sampling the input signal at a frequency twice higher than the frequency of the input signal. A larger oversampling ratio (k) will produce a more adequate representation of the digital bit stream. The more "1" or "0" that make up the bit stream, the better the digital approximation of the input signal. Figure 2 shows how oversampling at a sampling rate of k x fS/2 allows the modulator to extend the same amount of noise over a wider frequency range. This greatly reduces the noise floor in the frequency band of interest. The ideal signal-to-noise ratio (SNR) increases by 3dB for every 2 times the oversampling rate is increased. A larger SNR means that the incremental accumulation converter can better distinguish smaller changes in the analog input.




Figure 2: Oversampling reduces the noise floor in the frequency band of interest
Power: Power
noise floor after oversampling: the noise floor after oversampling
Orignal noise floor: the initial noise floor
Frequency: frequency
Oversampling ratio: oversampling ratio
By using the integrator in the modulator control loop for noise shaping, the incremental accumulating converter can accurately measure the analog input. The noise shaping process of the integrator is to force more noise to a higher frequency, as shown in Figure 3. Then, the digital low-pass filter removes the high-frequency part of the noise, which greatly improves the SNR. Digital filters can also be used to greatly reduce noise at 50 Hz, 60 Hz, or other unwanted frequencies.




Figure 3: The integrator forces the noise to a higher frequency
Signal Amplitude: signal amplitude
Digital Filter Rsponse: Digital filter response
Power: power
1. The integrator forces the noise to be outside the frequency band of interest;
2. Digital filter filters out high frequency noise
Frequency: frequency
Oversampling ratio: oversampling ratio
There will always be some noise caused by the input signal in the digital bit stream. But through averaging and filtering, the incremental accumulation ADC greatly reduces the noise floor. The oversampling rate and the "order" of the internal incremental accumulating modulator determine the level of noise. The term order refers to the number of integrators. For example, a 3rd order modulator contains 3 integrator stages.
Although increasing the number of integrator stages and increasing the over-sampling rate can further reduce the noise, stability is a big issue that needs to be paid attention to in the third-order or higher-order incremental accumulation converter. Once the incremental accumulation modulators become unstable, they will often not become stable again unless they are power cycled. All of Linear Technology’s incremental accumulation converters use a third-order modulator, and the modulator and filter are reset for each conversion. Even if the modulator enters an unstable state (this is likely to happen when the reference voltage is very low and the input signal is large), Linear Technology’s incremental accumulation ADC can recover itself without periodically switching the power supply In a steady state, other ADC products may not be able to do this.
After the modulator loop is stable and the noise is shaped by the integrator, the generated digital signal must be filtered and extracted. Decimation is to discard some samples, mainly to remove redundant signal information brought about by oversampling. If the oversampling rate is 256, then the ADC takes the average of 256 samples, and the decimator produces 1 digital output for every 256 samples. The digital signal generated after filtering and decimation is then output from the ADC in a serial format.
The digital output of the incremental accumulation ADC is as good as the reference source. A noisy reference is the main source of error in any data converter. The 1-bit DAC of the incremental accumulator modulator is biased by a positive reference voltage and a negative reference voltage. The positive (or high) reference voltage is generally the upper limit of the input range, and the negative (or low) reference voltage is generally the lower limit. Some of the positive and negative references of the incremental accumulation ADC are connected to the outside, while others connect the low reference to a common voltage, such as the ground voltage. Other ADCs can choose to use an internal bandgap reference or an external reference. Linear Technology’s incremental accumulation converter allows designers to change the reference and input common-mode voltage, ranging from ground to power supply voltage.
When choosing the incremental accumulation converter, the conversion clock and data delay are two important factors that need to be considered. The clock controls the internal timing of data processing and determines the conversion time. The conversion clock can be provided internally, or an external crystal or silicon oscillator can be used. However, since the digital filter does not suppress the oscillator frequency, it is advantageous to use the internal oscillator.
Due to data delay, the current output result lags behind the input by one sampling period. All Linear Technology's No Latency Delta SigmaTM converters are stable within one cycle, simplifying multiplexing applications.
Although the incremental accumulation ADC is very simple in nature, configuring this ADC is often a complicated process, such as writing a lot of instructions, balancing the complexity of the input stage, and selecting an external oscillator. Linear Technology’s incremental accumulation converter does not have calibration sequences, configuration registers, filter settling time and external oscillators, reducing the complexity of the design. Transparent offset and full-scale automatic calibration are performed in each conversion cycle to ensure high accuracy, and high accuracy ensures that the difference of 1 gram or 0.01 degree can be distinguished.