How to fully suppress the large AC ripple component that inevitably exists in the switching output?

An inexpensive way to achieve high-resolution digital-to-analog conversion is to combine the microcontroller's PWM (pulse width modulation) output with a precision analog voltage reference, CMOS switching, and analog filtering (reference 1). However, the design of PWM-DAC raises a big design problem: how to fully suppress the large AC ripple component that inevitably exists in the switching output? When you use a typical 16-bit microcontroller-PWM peripheral for DAC control, the ripple problem becomes particularly serious. Such high-resolution PWM functions usually have a longer period because of the reciprocal modulus of 2 16 16-bit timers and comparators. This situation will cause the AC frequency component to slowly slow down to 100 or 200 Hz. At such a low ripple frequency, if you use enough ordinary analog low-pass filtering to suppress the ripple to a noise level of 16 bits (ie –96 dB), the DAC stabilization time may become a full second or longer .

    The circuit diagram 1 avoids the problem of low pass through the combined differential integration, filtering 1, with the sample and hold amplifier, A 2, and the feedback loop operating in synchronization with the PWM period, T 2 in the diagram 2. If the integrator time constant is equal to the PWM cycle time (that is, R 1 × C 1 = T 2), and if the sampling capacitor C 2 is equal to the holding capacitor C 3, the filter can be acquired and stabilized to a new one in one PWM cycle DAC value. Although this method is difficult to make the final DAC completely "high-speed", the setup of 0.01 seconds is still 100 times better than the setup of 1 second. As important as speed, this improvement in settling time does not affect ripple attenuation. Theoretically, the ripple suppression of the synchronous filter is unlimited, but the actual limit is the non-zero charge injection from S 2 to C 3. Choosing a low-injection charge switch for S 2 and a capacitance of approximately 1 ?F for C 3 can easily lead to a ripple amplitude of microvolts.

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    Figure 1 The DAC ripple filter combines a differential integrator A 1 with a sample-and-hold amplifier A 2 in a feedback loop that runs synchronously with PWM.

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    Figure 2 DAC output is stable in one cycle.

    The optional feedback divider R 2 / R 3 provides flexibility in the output range of the DAC with a universal reference voltage source. For example, if R 2 = R 3, a 5V reference voltage will produce an output range of 0 to 10V. Another advantage of this span adjustment method is that the output ripple remains independent of the reference amplification.