A test method for measuring ADC conversion error rate

It is human nature to make mistakes. But for the system's analog-to-digital converter (ADC), what kind of requirements can we put forward? We will review the scope of conversion error rate (CER) testing and the analysis of high-speed ADCs. Depending on the sampling rate and the required target limit, the ADCCER measurement process may take weeks or months. To achieve a high confidence level (CL), testing is often required after the first error (Redd, 2000). For those systems that require low conversion error rates, efforts are needed to quantify them in detail. After everything is done, we can determine a high-confidence error rate—better than 10-15. Many actual high-speed sampling systems, such as electrical test and measurement equipment, life system health monitoring, radar, and electronic warfare countermeasures, cannot accept high ADC conversion error rates. These systems look for extremely rare or extremely small signals on a wide noise spectrum. False alarms may cause system failure. Therefore, we must be able to quantify the frequency and magnitude of the high-speed ADC conversion error rate.

CER and BER
First, let us clarify the two major differences in the description of the error rate. The conversion error rate (CER) is usually the result of incorrect judgment of the ADC on the analog voltage sampling. Therefore, compared with the full-scale range of the converter input, the corresponding digital code is also incorrect. ADC's bit error rate (BER) can also describe similar errors, but for our discussion, we define BER as a pure digital reception error; if there is no such error, then the converted code data is correct. In this case, the correct ADC digital output cannot be correctly received by downstream logic devices such as FPGA or ASIC. The extent of code errors and how often they occur are what will be discussed in the rest of this article. It may be difficult to grasp the ADC conversion error just by reading the technical parameters in the data sheet. Using a single piece of data in the converter data sheet, of course, some estimation of the conversion error rate can be made, but what exactly does this data quantify? You have no way of judging how much sample deviation can be considered an error, and you cannot determine the confidence of experimental measurements or simulations. The definition of "error" must be limited to the amplitude corresponding to the known frequency of occurrence

Error source
There are many error sources that can cause ADC conversion errors, both internally and externally. External error sources include system power glitches, ground bounce, abnormally large clock jitter, and possibly erroneous control commands. The recommendations and application notes in the ADC data sheet usually describe system layout practices that avoid these external issues. The internal error source of ADC can be mainly attributed to the residual processing transfer between stages in the metastable state (Beavers, 2014) or the analog domain, as well as the output timing error in the digital domain and the physical layer. The ADC design team must analyze these challenges during the device development process.

Figure 1. For each bit of analog resolution at full scale, an ideal ADC sample has a single digital output (left image). An example of actual ADC output behavior (right image) shows the relationship between internal and external noise

Some ambiguity in relation.

Figure 3. When the input is open or floating, the ideal ADC will sample and output a mid-level offset code, as shown in the histogram on the left. The actual ADC will have input-referred noise, which should appear as a Gaussian-shaped curved histogram on a logarithmic scale (right side).

The integral nonlinearity (INL) of an ADC is the transfer function of the actual sample code relative to the ideal output within the full-scale input range of the ADC (Kester, 2005). The ADC data sheet usually also explains this information and gives its curve. The deviation from the ideal code is usually expressed by a certain number of LSBs. The following is an example of an INL curve. Although it reflects a certain amount of error, in most 16-bit or lower resolution high-speed ADCs, INL usually only has 0 to 3 codes. It is not the main contributor to the actual error rate of the converter.

Figure 4. INL curve example, measured on all ADC codes, the error is ±1LSB or ±1 code compared to the ideal sample, which is basically negligible for the ADC conversion error.

testing method
For long-term CER detection, the test method can use a very low ADC input frequency (relative to the clock rate). A straight line is formed between any two adjacent sample points, and the slope of the sine wave can be approximated to the slope of the straight line. Similarly, input frequencies slightly higher than the sampling rate will alias into low frequencies. In this case, there is a predictable ideal solution to keep each adjacent sample within ±1 code of the previous sample. The input signal frequency and the encoding sampling clock frequency must be locked to maintain predictable phase alignment. If this phase is not a constant value, the alignment will be out of phase and the measurement data will be useless. Therefore, in order to calculate the ideal conversion result, the sample (N+1)–sample(N) should differ by one code and the amplitude should not exceed 1. The sources of small predictable conversion errors inherent in all ADCs include integral nonlinearity, input noise, clock jitter, and quantization noise. All these noise contributions can be accumulated to obtain a difference limit. If this limit is exceeded, the error will be regarded as coming from two adjacent conversion samples. The output code number of a 16-bit ADC is 24 or 16 times that of a 12-bit converter.

Therefore, the extended resolution affects the number of codes used to limit the conversion error rate test. When everything else is the same, the limit of the 16-bit ADC will be 16 times wider than the 12-bit ADC. The ADC built-in self-test (BIST) function can be used to determine the error threshold based on thermal noise, clock jitter, and other system nonlinearities. When the error limit is exceeded, a specific sample and its corresponding sample number and error margin can be marked in the ADC core. The big advantage of using the internal BIST is that it defines the error source in the ADC core itself, eliminating the error caused by the received bit error that is exclusive to the digital data transmission output. Once the error threshold is clear, complete system measurements involving the ADC, link, and FPGA or ASIC can be performed to determine the full component CER.

Figure 5. The relationship between ADC conversion error rate and its thermal noise can usually only be obtained through transistor-level circuit simulation. The figure above is an example of a 12-bit ADC. To achieve a CER of 10-15, it must be able to withstand 8Σ thermal noise.

Now look at how to calculate the thermal noise contribution (Brannon, 2003).

SNR=20log (VSIGNAL/VNOISE)

VNOISE=VSIGNAL&TImes;10^(–SNR/20)

In order to get the rms noise of the ADC, VFULLSCALE must be adjusted:

VNOISE=(VFULLSCALE/(2&TImes;(2)&TImes;10^(–SNR/20)

Use the following formula to calculate the thermal noise limit of AD9625. It is a 12-bit 2.6GSPSADC with a design full-scale range (FSR) of 1.1V, SNR of 55, and an aliased input frequency of 2.508MHz. Thermal noise limit=8&TImes;VINpp×10^(SNR/20)/2√(2)=3.39mV~±12 codes.

In this example, for the 10-15 error limit, the 8Σ distribution of thermal noise alone can contribute ±12 more codes. This should be measured for the ADC’s total input-referred noise measurement.

test. Note: The input-referred noise in the data sheet may not be measured based on a large enough sample size (for 10-15 tests). Input-referred noise includes all internal noise sources, including thermal noise.

In order to clarify the boundary to include all noise sources as much as possible, including test equipment, we use internal BIST to measure the error margin distribution. Use the internal BIST of AD9625 to

2.5GSPS operation, aliasing AIN frequency of 80kHz, close to ADC full scale, using nominal power supply and temperature conditions to perform CER measurement, a period of 20 days.

It is assumed that all ADC processing for converting an analog voltage to a digital representation is ideal. The digital data still needs to be transmitted, and in the downstream FPGA or ASIC of the signal chain

Received in the next processing. This digital confusion is usually defined by bit error or bit error rate. However, the comprehensive characteristics of the ADC’s data eye diagram output can be found on the PCB

The end of the trace is measured directly and compared with the JESD204B receiver goggles to get a good understanding of the output quality (Farrelly, Loberg 2013)1.

When running at 2.6GSPS within 1Σ, in order to establish a CER of 10-15, 10 to the 15th power samples, it is necessary to run this test continuously for 4.6 days. For larger Σ, it is necessary to establish more

With high confidence, this test will take longer to run2. The test requires a very stable test environment and a clean power supply. If there are any glitches in the voltage source of the converter under test,

Being suppressed will cause measurement errors, and the test will have to start all over again.

Figure 6. Using long-term histograms of ADC samples compared to ideal output codes, we can detect any deviations that exceed the calculated limits. The histogram is similar to the Poisson distribution chart.

system
After knowing the CER of a single converter, we can calculate the error rate of a synchronous system with many converters. Many system engineers will ask: In a large and complex system that uses a large number of ADCs, what is the cumulative ADC conversion error rate?

Therefore, for a multi-signal acquisition system, the second consideration is to determine the conversion error rate of a series (rather than one) of the converters. At first glance, this may seem like a daunting task. Fortunately, after the CER of a single ADC is measured or calculated, it is not that difficult to extrapolate this error rate to multiple ADCs. In this way, the function becomes a probability expansion equation based on the number of converters used in the system.

First, find the probability that a single converter will not make an error. It is only slightly smaller than 1, that is, 1 minus the error rate value (1-CERSINGLE). Secondly, how many ADCs there are in the system, multiply the probability as many times as (1–CERSINGLE)#ADCs. , Subtract 1 from the above value, you can get the error rate that the system will make mistakes. We get the following equation:

CERMULTIPLE=1–(1–CERSINGLE)#ADCs

Consider a system that uses 99 ADCs and a single ADC has a CER of 10-15.

1–CERSINGLE=0.999999999999999

CERMULTIPLE=1–(0.999999999999999) 99=

9.8999999999995149000000000799095×10–14 (~about10–13)

It can be seen that the current value of CERMULTIPLE is almost higher than that of CERSINGLE

(10-15) 100 times larger. It can be seen that the conversion error rate of a system with 99 ADCs is roughly equal to the CER of a single ADC multiplied by the number of ADCs in the system. Fundamentally, it is higher than the conversion error rate of a single ADC, which is limited by the conversion error rate of a single ADC and the number of converters used in the system. Therefore, we can conclude that a system containing many ADCs will significantly increase the total conversion error rate compared to a single ADC.

Figure 7. The CER of a system using multiple converters is proportional to the CER of a single converter multiplied by the number of ADCs.

Determining the ADC conversion error can be difficult, but it is still achievable. The first step is to determine roughly how large the conversion error in the system is. Then a set of appropriate bounded error limits needs to be determined, including benign sources of non-linearity for expected ADC operation. , The specific measurement algorithm can achieve most or all of the tests. The measurement results can be extrapolated beyond the test limits to obtain additional approximations.