Electronic engineer's measurement "artifact"-how to design the arbitrary waveform generator?

Speaking of signal sources, electronic engineers must be very familiar with it. Like spectrum analyzers and oscilloscopes, it is a standing test instrument for product development in the electronics and information communication fields. A signal source is also called a signal generator. It is an electronic device that can generate electronic signals in the analog or digital domain. It has many different types, including function generators, RF and microwave signal generators, arbitrary waveform generators, and digital Pattern generator and frequency generator. Among them, the arbitrary waveform generator (AWG) has a very common and extensive application in the application field of analog signal or analog-digital mixed signal.
The most important thing in the design of arbitrary waveform generator is the ADC, DAC, operational amplifier, clock and power supply used. The correct selection of these devices can ensure that the system can provide lower spurs, noise and other key indicators. Analog technology manufacturer ADI has recently launched a new arbitrary waveform generator solution design reference, focusing on applications with a bandwidth below 300MHz. Using ADI’s advanced DAC technology, it provides lower spurious and noise indicators, which can solve the user’s chip selection Type confusion can also be foreseen in advance of design difficulties, and countermeasures can be made in the early design.
How to break the six major design pain points of arbitrary waveform generator?
Arbitrary waveform generator is one of the widely used universal instruments in the field of modern electronic testing. It uses high-speed DAC to convert the waveform file in the memory into actual waveform signal. The waveform file can be flexibly customized by the user, and the waveform characteristics are only limited by Its sampling rate bandwidth. Due to the existence of various interferences and changes in the environment, devices that actually operate in the actual electronic environment often have various signal defects and transient signals in their circuits, such as overpulses, spikes, damping transients, and frequency mutations. The arbitrary waveform generator can generate various ideal and non-ideal waveform signals, so it can be used in various hardware-in-the-loop simulations. For example, the reproduction of a car crash experiment, or the generation of high-speed analog signals to test the function of a certain chip. From simple sine wave generation to more complex AM/FM modulated signals, to more complex QAM modulated signals, there are applications for arbitrary waveform generators.
Most of the previous waveform generators used DDS (Direct Digital synthesizer) technology, which was first proposed by American scholars J.Tiemey, C.M.Rader and B.Gold in 1971. However, because the internal data structure of the DDS chip is fixed, it is not easy to change, so that the types of output waveforms are limited, the configurability and flexibility of the system are also restricted, and the power consumption is still relatively large, and the cost is relatively high. . Later, with the increasing development of field programmable gate array FPGA technology, more and more people began to pay attention to the use of FPGA technology to complete the design of arbitrary waveform generators. In the design process, the following six design difficulties deserve special attention:
High speed and large
There are many high-speed operational amplifiers, but they can output very few large amplitudes. Therefore, some high-speed signal amplifier circuits need to be implemented with discrete transistors, which greatly increases the difficulty of design.
Flat passband characteristics
If the passband flatness is not good enough, it will cause waveform distortion. Sine waves can use amplitude compensation to optimize flatness, but arbitrary waveforms cannot do this. Therefore, a signal source with high performance must have excellent hardware circuits. Flatness index.
low noise
If you want to generate a signal of 1mVp-p or even smaller amplitude, the signal-to-noise ratio index is a problem that cannot be circumvented. It needs to be considered in the design of the entire product from beginning to end.
Low jitter square wave, pulse wave
The square wave generated by the pure DDS architecture will have more 1/fsa jitter when outputting at non-fsa/n frequencies. That is a huge visible jitter, so it is usually unacceptable. It must be removed by some special methods. Kind of jitter. The point-by-point output waveform generator with variable sampling rate does not have this problem.
The jitter between the trigger channel and the analog channel
The jitter between the trigger output and the analog channel output mainly comes from the alignment of the digital signal and the analog signal. The trigger output comes from the digital signal generated by the FPGA. When it is output at a frequency other than fsa/n, it cannot be aligned with the zero-crossing point of the analog signal phase, so periodic jitter will occur. The jitter between the trigger input and the analog channel output is due to the fact that the external trigger input signal is random. In most cases, it cannot be aligned with the FPGA sampling master clock. Therefore, there is obvious jitter when switching from the trigger signal sampling to the analog output.
Two-channel phase alignment
The clock originally from the same clock chip is supplied to two DACs, and the layout delay is better controlled, which makes it easy to achieve phase synchronization of the two channels. But in fact, there is a DLL inside the high-speed DAC, and the initial phase may change after each power-on, so it is still more challenging to achieve ps-level phase alignment. For this problem, it is much simpler to use a dual-channel DAC, but the channel isolation index may become worse.
ADI high-performance arbitrary waveform generator is like this
The arbitrary waveform generator system block diagram provided by ADI for reference is a common FPGA+DAC based on the DDS architecture. For example, to implement a 2.5GSPS AWG, you need to run 10 groups of DDS in parallel inside the FPGA. The clock of each group of DDS is 250MHz, and the initial phase interval of each group is 36 degrees. Each group of DDS uses the same waveform look-up table LUT, and the generated The data is converted into two groups of high-speed 1.25Gbps 14-channel LVDS data and sent to the DAC.

Figure 1: AWG system block diagram.
AWG usually has high requirements on the jitter index of the signal, so an ultra-low jitter clock chip, such as LTC6952 or HMC7044, is recommended. If the AWG is to be designed as a channel floating output, then the MCU is suitable to be placed on the ground of the chassis connected to the ground, so that external interfaces such as GPIB/USB/LCD can be simplified (no isolation design required). AWG floating output capability is a relatively safe design, even if the object under test (DUT) does not work above the ground reference level, it will not damage the DUT or the AWG itself.
The design of the trigger input and output port has a certain degree of difficulty, which is mainly reflected in how to remove the jitter between the output signal of the analog channel. The trigger input signal port may be an analog signal, so a high-speed comparator is needed to convert it into a digital level, such as ADCMP605, which is directly differentially output to the FPGA, which can reduce the crosstalk to the analog channel caused by the long signal path.
The power topology of the AWG is mainly based on high integration and low noise power chips. For signal source products such as arbitrary waveform generators, the lower the noise, the better, and the higher the signal-to-noise ratio, the better. However, most of the power supply comes from ac to dc or dc to dc power supply, which has a lot of switching noise and high-frequency spikes. Therefore, the PSRR index is mainly considered for the selection of LDO. The ripple of dc and its harmonics. The recommended LDO is LT3045-1, which still has a PSRR above 50dB at 10MHz. For FPGA applications where the power supply current is relatively large and the number of voltage paths is relatively large, it is recommended to use power modules such as LTM4643/LTM4644 to simplify the layout area and design difficulty, and one piece can meet the power supply requirements of most FPGAs.

Figure 2: AWG power supply topology diagram.
  in conclusion
With the continuous development of communication technology and radar systems, more and more requirements are put forward for the frequency stability, spectrum purity, frequency range and number of output frequencies of the signal source, and the shape of the signal waveform. The arbitrary waveform generator can not only generate standard waveforms such as sine waves and square waves, but also need to generate arbitrary waveforms according to requirements. The output waveform is of good quality, wide frequency range, high frequency stability, accuracy and resolution, fast frequency conversion speed and frequency The output waveform phase is continuous during conversion, etc.