How to do the SCR zero-crossing detection speed regulation program? How to design the hardware and software?

LVDS has been widely used in interface devices, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs). Systems using LVDS have successfully realized high-speed interconnection. However, not all LVDS I/O interfaces have good performance. For example, the LVDS I/O of some ASICs or FPGAs may not be as suitable for driving differential traces on the PCB as the LVDS I/O in standard devices. Due to the PCB layout problems, the signal transmission quality of well-designed standard devices even deteriorates. When using ASIC or FPGA as a system component, it is sometimes impossible to place the device as close to the connector as possible, which will cause the trace to change, the reflection to increase, and the loss to increase. In order to eliminate the problems in interconnection, National Semiconductor has introduced a series of compact buffers. The function and application of its LVDS ultra-high-speed crosspoint switch SCAN90CP02 will be introduced in the article.

1. Introduction to SCAN90CP02

SCAN90CP02 circuit is a 1.5Gb/s 2x2 low voltage differential signal transmission analog crosspoint switch introduced by National Semiconductor. Its high-speed data path and flow-through pins can achieve the jitter inside the circuit. When the signal is transmitted on the lossy backplane and cable, its configurable pre-enhancement function (0/25/50/100% optional) can overcome the influence of external ISI (Inter Symbol Interference) jitter. Its differential input can be connected to LVDS and Bus LVDS signals, and can also be connected to signal levels such as common mode logic (CML) and low voltage positive emitter coupled logic (LVPCL). SCAN90CP02 needs to use a non-block cross-point structure, which can be configured as a 1:2 clock or data distributor, 2:1 redundant multiplexer, crossover function, and double buffers for signal enhancement and short-line hiding. Figure 1 is the internal block diagram of SCAN90CP02.

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SCAN90CP02 integrated IEEE 1149.1 (JTAG) and 1149.6 test input circuit TAP (Test Access Port) support single-ended LVTTL/CMOS and differential LVDS PCB interconnection testability. These functions help to shorten the test time and reduce the cost of testing and development. The circuit uses 3.3V power supply, CMOS technology and LVDS I/O to ensure that it achieves high performance and low power consumption within the entire industrial temperature range (-40°C to +85°C).

SCAN90CP02 can truly eliminate jitter, thereby improving the reliability of the system, and enabling users to use lower-cost lines to achieve interconnection. Because SCAN90CP02 has a pre-enhancement function, it can not only perform normal switching functions, but also can be used as a buffer to amplify the LVDS signals of the existing FPGA, ASIC, and serial/deserializer (SerDes). In addition, the LVDS output of this circuit does not support multidrop BLVDS environments.

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The features of SCAN90CP02 are as follows:

●The transmission rate of each channel is up to 1.5Gb/s.

●Low power consumption, in the dual repeater mode, the current at the rate is only 70mA.

●Low output jitter.

●The configurable pre-enhanced function (0/25/50/100%) can drive lossy backplanes and cables.

●With a flow-through pin lead.

●LVDS/BLVDS/CML/LVPECL input, LVDS output.

●Applicable to IEEE 1149.1 and 1149.6 standards.

●Single power supply 3.3V power supply.

●The input and output can be individually controlled to reduce power consumption.

●Industrial temperature range (-40℃ to 85℃).

SCAN90CP02 is available in 28-pin LLP package or 32-pin LQFP package.

The pre-enhancement function of the circuit is used to compensate for long-distance transmission or lossy transmission media. In order to make power consumption, the circuit provides independent pins for each output. And the pre-increment function is programmable equipment.

2 Application of SCAN90CP02

In the author's design project, it is necessary to transmit data at a rate of up to 600Mb/s, and the transmitter and receiver complete tasks such as data transmission and reception, modulation and channel matching. In order to test the quality of the data transmission of the entire communication system, the author additionally designed a high-speed bit error rate tester. The tester is composed of 3 circuit boards, namely the clock generating board, the sending board and the receiving board. A SCAN90CP02 is used on the clock generation board and the distribution board. One is to make the output signal on the circuit board as close as possible to the connector, to reduce the wiring pressure on the circuit on the board, and to make its position more free; the other is to complete the level The conversion task is to convert the LVPECL level to the LVDS level; the third is to compensate the loss of the wiring to ensure that the signal has a better transmission quality. The block diagram of the BER tester is shown in Figure 2. The figure highlights the connection mode of SCAN90CP02. The various circuit boards in the tester are described in detail below.

(1) Clock board. The SCAN90CP02 of the clock board is configured as a 1:2 distributor mode, and EN0, EN1, SEL0 and SEL1 are all set to low level. The 300MHz clock signal generated by the clock board is LVPECL level, converted into 2 LVDS levels by SCAN90CP02, and sent to the sending board and receiving board of the BER tester respectively.

(2) Issue board. The development board is based on Xilinx's VirtexII series XC2V250 circuit, which is composed of some peripheral circuits and control circuits to complete functions such as pseudo code generation, data framing, and parallel-to-serial conversion. The output 600Mb/s data and 300MHz clock are sent to the transmitter through the connector through the SCAN90CP02 interrupt. SCAN90CP02 is configured as a dual-channel interrupter mode, SEL1 is set to high level, and other control terminals are set to level.

(3) Close the board. The receiving board is based on Xilinx's VirtexII series XC2V250 circuit, which is composed of some peripheral circuits and control circuits. Realize the functions of frame synchronization, data recovery, serial-to-parallel conversion, comparison counting and error statistics display.

The pre-enhanced control end of SCAN90CP02 uses DIP switches to select high and low levels to increase design flexibility.

3, concluding remarks

In many applications, especially when high-loss backplanes and cables are used for connection, some circuits (such as ASIC and FPGA, etc.) often have insufficient drive capabilities, which requires the use of circuits with pre-enhancement functions (such as SCAN90CP02) to pre-load the signal Amplify, this not only can ensure that the receiver gets enough input signal voltage, but also can increase the transmission distance and improve the signal quality. Especially when the LVDS transmission method is adopted, its anti-interference ability is greatly enhanced, and electromagnetic radiation is also reduced.