An article about MEMS wafer-level test systems

Micro-Electro-Mechanical System (MEMS) belongs to the 21st century cutting-edge technology, which is the general term for MEMS accelerometer, MEMS gyroscope and inertial navigation system. The feature size of MEMS devices ranges from millimeters, micrometers, and even nanometers, involving many disciplines such as mechanics, electronics, chemistry, physics, optics, biology, and materials. In terms of product development, it can significantly improve the degree of equipment lightweighting, miniaturization, miniaturization and integration, so the application is extremely wide. The difference between MEMS product manufacturing and classic IC is that it contains mechanical parts, and the packaging process accounts for most of the cost of the entire device. If device failure is detected after the final packaging, it will not only waste cost, but also waste research and development (R&D), process and Foundry time, therefore, wafer-level testing of MEMS products can reduce product costs and accelerate time to market in early product functional testing, reliability analysis, and failure analysis, which is critical to the industrialization of MEMS.

Wafer-level testing technology is applied to the three stages of the full cycle of MEMS product development: (1) Product development (R&D) stage: to verify the feasibility of device work and production, and to obtain early device features. (2) Product trial mass production stage: verify the ability of the device to mass produce with a higher yield. (3) Mass production stage: to reduce throughput and reduce costs. This article analyzes the hardware and system technology status of domestic and international MEMS wafer-level test systems, referring to RM 8096 and RM 8097 in the following table, and provides solutions to existing domestic problems.

Demystified: An article for you to understand MEMS wafer-level test system

MEMS wafer level test system hardware

1. Test System

As mentioned in the introduction, the yield rate of general MEMS products is much lower than that of IC products. Cost analysis found that 60% to 80% of the manufacturing cost comes from the packaging stage. In Figure 1, when the yield rate is 50%, wafer-level testing is used. The chip can save 30% of the total cost. It can be seen that the use of wafer-level testing technology can greatly reduce the cost of MEMS mass production and improve device reliability.

Demystified: An article for you to understand MEMS wafer-level test system

Figure 1 Comparison of total cost with and without wafer-level testing

Internationally mainstream MEMS developers, such as Texas Instruments (TI), Analog Devices (ADI), Freescale Semiconductor (Freescale), Silicon Microstructures (SMI) in the United States, Robert Bosch in Europe, STMicroelectronics (ST), Japan's Toyota Denso (DENSO), Omron (Omron), etc. are equipped with MEMS wafer-level products supporting test systems.

Domestically, certain universities have established wafer-level test systems to serve their own MEMS production lines, such as Tsinghua University, Peking University, Fudan University, Southeast University, Harbin Institute of Technology, etc.; some research institutes, such as China Electric Power 49 Schools, 13 schools, 26 schools, 46 schools, etc. The test system has different structures and functions according to the characteristics of the products. Among them, the aerospace cutting-edge company has obvious advantages in the development of MEMS wafer-level test systems, and launched the LS1100 series MEMS wafer full-parameter automatic test system. Test products include flow meters, accelerometers, gyroscopes, etc. The test system consists of a probe station and a series of measuring instruments to measure the dynamic and static parameters of the wafer. The system test rate reaches 8s/chip; the wafer is 6 in (1 in=2.54 cm); the parameters include tiny capacitance (10aF), resistance (1Ω～1GΩ), natural frequency (20kHz), quality factor (200000), bandwidth ( 10kHz) 5 types in total, with an accuracy of ±1%.

2. Dedicated probe card

The probe card is a necessary means to connect the chip pins and standard instruments, and is a part of the wafer-level chip automatic test.

Internationally, as early as 1995, Beiley M et al. proposed a thin film probe card with an array structure. The probe card used polyimide as a film and built the probe into the film; in 2002, Park S Et al. proposed that the cantilever beam structure probe card developed by using type III silicon wafers can withstand a certain contact force and produce sufficient displacement of the probe tip. Therefore, the current internationally common probe card form is this form.

Domestically, manufacturers use MEMS cantilever beam chip test probes to carry out wafer-level testing. The main performance of the probe card includes mechanical and electrical characteristics. The mechanical properties of the probe card are mainly measured by detecting the elastic coefficient of the cantilever beam. In recent years, nanoindentation technology has become an important method for testing the mechanical properties of MEMS structures. Using the Nano Indenter XP nano indentation system, a gradually increasing contact force is applied to the probe tip, and the force-displacement curve can be obtained. The force-displacement curve of the loading and unloading process almost coincides, indicating that the cantilever beam is in the entire force process. There is no plastic deformation. The electrical characteristics of the probe card can be tested using the semiconductor probe test bench. In the open circuit state, a 20 mV DC voltage is applied to the tips of two adjacent cantilever beams, and the measured leakage current is only 0.04 pA, that is, the insulation resistance between adjacent cantilever beam probes is as high as 500GΩ in the open circuit condition. When the probe tips are shorted to each other, the path resistance can be measured to be about 1.6 Ω. In other words, for a cantilever beam, the interconnection resistance between the tip of the probe card and the lead point on the front of the probe card is only 0.8 Ω, which has reached the basic requirements of current chip testing. In addition, a semiconductor parameter tester (HP4284A) was used to test the parasitic capacitance between two adjacent probe lead pads, and the result was only 0.02-0.03pF. In summary, domestic probe cards of this type meet the requirements of batch testing of MEMS wafer-level test systems in terms of mechanical and electrical properties.

MEMS wafer level test technology

1. International Status

Foreign MEMS development attaches great importance to the construction of basic technology, especially testing technology, and has established corresponding laboratories, such as MCNC in the United States, SANDIA National Laboratories, and BOSCH laboratories in Germany. In addition, MEMUNITY, established in 2003, is an international organization in the field of microsystem testing technology, mainly researching the measurement and testing of micromechanical products. By studying the devices used in wafer-level testing technology, reduce the production cost of MEMS products and promote the commercialization of microelectronic mechanical systems. The main goal of the organization is to understand the progress of the measurement technology of the mechanical and electrical performance of the next generation of micro-electromechanical systems, and to discuss wafer-level testing strategies and standardization issues. A number of research results have been achieved in the field of wafer-level testing technology. Recently, MEMUNITY completed the collaborative PAR-TEST project. The result of the project is the development of an integrated wafer-level MEMS device test system. The test system is a semi-automatic detection system (SUSS PA200), which has automatic positioning and wafer drawing functions. It drives the diaphragm through an electrostatic probe card and uses a laser Doppler meter to measure out-of-plane motion. The characteristic parameters can be extracted by measuring the intrinsic frequency, and the obtained data results are used to optimize the device design and manufacturing process, as well as to determine the good or bad die test.

2. Current domestic situation

my country's MEMS wafer-level testing technology research began in the early 1990s. After 20 years of development, several areas with relatively concentrated research forces have initially formed, such as Beijing and Tianjin, East China, Northeast China, Southwest China, and Northwest China. Since the object of MEMS wafer-level testing is a three-dimensional microstructure, its testing technology is very different from traditional IC wafer testing. The difficulties are mainly reflected in three aspects: the test chip is a pure mechanical structure without any circuit components; The signal of the chip is very weak. For example, the capacitance is only aF, which is difficult to extract and has poor anti-interference ability. In addition to static tests, the test items also require a large number of dynamic index tests, such as resonance frequency, damping coefficient, bandwidth, etc. As mentioned in the previous article, the test technology of the cutting-edge domestic aerospace is in the domestic position, especially the use of low parasitic parameter probes, special small capacitance detection circuits, detection circuits and probe card integration, shielding and vibration isolation, and parasitic parameter compensation five technologies to reduce parasitics The influence of the parameters on the capacitance to be measured, to realize the detection of small capacitance.

MEMS test system verification

At present, the domestic MEMS wafer-level test system mainly carries out the measurement of the electrical parameters of the wafer, and the international research for this department has become mature, and a large number of studies have been carried out on the mechanical parameters of chips and products. Elaboration.

1. International Verification Scheme

Internationally, Janet Cassard of the National Institute of Standards and Technology of the United States proposed to provide a five-in-one reference material (RM) to solve the verification of MEMS wafer-level test systems. This standard material is a chip with an independent test structure. This test structure obtains material and spatial characteristics through five standard test methods. Customers can trace the source by comparing the test data of the standard substance in the testing system of this institution with the data obtained in the same test system of the NIST (National Institute of Standards and Technology). In addition, five-in-one MEMS can also be applied to process measurement and verification, local measurement of customer systems, laboratory comparisons, disputes and arbitration, and instrument calibration.

MEMS five-in-one chips are NIST standard materials used to measure space and material properties. They are divided into RM8096 and RM8097. RM8096 is made by 1.5μm compound semiconductor (CMOS) process line and micro-machining etching. It is reported that each layer of this standard material is a compound oxide layer. RM8097 is made by the back etching technology of multi-layer surface micromachining MEMS polysilicon. Among them, the characteristics of the second layer of polysilicon are publicly reported.

"Five standard test methods" are used to test the characteristics of MEMS five-in-one chips: Young's modulus, step height, residual strain, strain gradient, and plane length. Among them, the measurement methods of Young’s modulus and step height have been reported in "International Semiconductor Instruments and Materials (SEMI)", and the measurement methods of residual strain, strain gradient, and plane length are provided by "American International Measurement & Materials Association". (ASTM)" It is publicly reported that each of the above measurement methods has a series of accuracy and correction data.

"Eight technical characteristics" are representative and typical parameters in the standard material certificate, that is, the five mentioned in the previous description plus the following three: residual stress, stress gradient, and beam thickness. Residual stress and stress gradient are calculated by Young's modulus test method; beam thickness characteristics are obtained by using RM8096 based on electro-physical technology, plus RM8097 through opto-mechanical technology, using step height measurement method (in NIST special issue SP260— Mentioned in 177). Therefore, five test methods can be used to obtain eight technical characteristic parameters.

As mentioned in each test method listed, the test method of Young's modulus uses an optical vibrometer, a laser interferometer of a stroboscope, or similar instruments. The other four measurement methods use optical laser interferometers and needle profilometers or similar instruments. The MEMS calculator can perform data analysis on MEMS characteristic parameters. There is a verification area at the bottom of each data analysis form. If all relevant units display "OK", the data verification is passed; otherwise, the specific area will prompt "correct data and recalculate".

Each "five-in-one chip" comes with a standard material certificate, including the corresponding data analysis form, five measurement methods and NISTSP260-177. The attached corresponding data analysis form gives the special test structure of the corresponding measurement method, and includes the original data used to obtain the measurement results in the NIST standard material certificate. SP260 is a comprehensive MEMS 5-in-1 user manual; it lists the same SEMI or ASTM standard measurement method based on the same measurement structure of NIST; at the same time, it recommends a measurement method that can be compared with the NIST standard material certificate. Verify the correctness of the standard measurement method of user files.

2. Domestic verification methods

my country has already purchased or established multiple MEMS wafer-level test systems, and the verification methods are still at a blank stage. Since there are no standard materials and standard samples for this kind of special test equipment in China, the accuracy and consistency verification of the test system has not yet been resolved, and it remains at the level of "single instrument split measurement", and no systematic testing has been carried out. In the overall calibration work, the various system parameters cannot be traced to the probe end face, and it is difficult to ensure the accuracy and consistency of the MEMS product parameters, laying hidden dangers for product quality.

Gap

Regardless of the hardware composition or the comparison of testing technology and verification methods, there is still a certain gap between us and the international community, which is mainly reflected in three aspects:

1) Lack of standardized testing hardware systems. Despite the many benefits of early testing, it is difficult for most manufacturers to find standardized, independently operating test systems, and there is no single test standard to follow. MEMS testing must be performed by adding appropriate modules for non-electrical excitation input measurement and non-electrical signal output detection. Wafer probes can be expanded into an open and general test platform, which can be easily adjusted according to test needs. The entire open platform can be used to test different products such as pressure sensors, micro microphones and micro mirrors.

2) Testing technology needs to be improved. In terms of excitation signal, in addition to electrical excitation and electrical testing, the device may also need acoustic, luminescence, vibration, fluid, pressure, temperature, chemical or dynamic excitation input; in terms of test platform, the device may need an open platform and Only by testing in a controlled environment can the device be protected from environmental damage or the device can be properly stimulated in the packaged environment. Wafer-level testing of MEMS devices can be performed in the vacuum required for testing or in a special gas environment, requiring a controllable testing environment.

3) The system verification means is blank. In view of the microscopic nature of wafer-level testing and the lack of standard samples for probe ends, the current domestic test systems cannot transmit the value of accuracy from the aspect of accuracy, which makes it difficult to ensure its traceability and cannot perform wafer-level testing. It is difficult to guarantee the rationality and accuracy of chip removal due to its superiority.

Concluding remarks

Since the birth of micromechanical technology in the 1960s, MEMS wafer testing technology has gradually matured with the development of MEMS products. With the requirements of practicality, high reliability, and low cost of manufacturing devices, the following development trends have appeared in test systems: The future MEMS wafer-level test system will develop towards a standardized and modular open platform; in terms of parameter-level metrology, there is an urgent need to use MEMS or IC technology to develop high-stability standard samples, which is an effective calibration solution; product-level testing On the one hand, referring to NIST's MEMS five-in-one test chip, it is urgent to form a modular standard test platform by adding peripheral circuits to the MEMS chip to solve the test problems under non-electric signal excitation and develop standard materials that meet the corresponding excitation signal test. Integrate with the international NIST standards, further catch up with the international level, and improve the overall level of China's MEMS wafer-level testing.