Design of high-end current detection circuit with over-voltage protection function

After a transient occurs, or when connecting, disconnecting, or shutting down the monitoring circuit, the high-side current monitor may experience an overvoltage condition. The circuit shown in Figure 1 uses an ADA4096-2 operational amplifier connected as a differential amplifier with overvoltage protection to monitor the high-side current. The ADA4096-2 has an input overvoltage protection function. For voltages higher than 32 V and lower than the supply rail, no phase reversal or latch-up will occur.


    Figure 1. High-side current detection with input overvoltage protection (Schematic diagram: not all connections and decouplings are shown)


    The circuit uses an adjustable low dropout 500 mA linear regulator ADP3336 to supply power, which can also be used to power other parts of the system if required. When set to 5 V output, the input voltage range is 5.2 V to 12 V. In order to save power, the current detection circuit can be turned off by setting the ADP3336 SD pin low, while the power supply (such as solar panels) can still work. This will apply voltage to the input of the unpowered ADA4096-2, but no latch-up or damage will occur under input voltages up to 32 V. If a lower throughput rate is required, the AD7920 can also be shut down between samples. The AD7920 consumes 5 µW in shutdown and 15 mW in power up. Under operating conditions, the ADA4096-2 only requires 120 µA. When the operating voltage is 5 V, the power consumption is only 0.6 mW. In shutdown mode, the ADP3336 consumes only 1 µA.


    Figure 2. Schematic diagram of ADA4096-2 principle


    Circuit description
    This circuit is a classic high-end current detection circuit topology, using a single detection resistor. The other four resistors (dual channel 1 kΩ/20 kΩ voltage divider) are in the thin film network (to achieve ratio matching) to set the gain of the differential amplifier. This will amplify the difference between the two voltages generated on the sense resistor and suppress the common-mode voltage:
    VOUT = (VA – VB) (20 kΩ/1 kΩ)
    Figure 2 shows the schematic diagram of the ADA4096-2. The input stage contains two parallel differential pairs (Q1 to Q4 and Q5 to Q8). As the input common-mode voltage approaches VCC- 1.5 V, Q1 to Q4 turn off when I1 reaches the compliance voltage. Conversely, as the input common-mode voltage approaches VEE+ 1.5 V, Q5 to Q8 turn off when I2 reaches the compliance voltage. This topology can achieve input dynamic range because the amplifier can still handle the input at 200 mV (room temperature) outside the supply rails.
    As with any rail-to-rail input amplifier, the VOS mismatch between two input pairs determines the amplifier's CMRR. If the input common-mode voltage range is kept within 1.5 V of each supply rail, transitions between input pairs can be avoided, thereby improving CMRR by approximately 10 dB.
    The ADA4096-2 input protects the device from input voltage shifts that exceed 32 V for each supply rail. This feature is particularly important for applications that have power sequencing problems, which can cause the signal source to be active before the amplifier power is applied.
    Figure 3 shows the input current limiting capability of the ADA4096-2 provided by a low RDSON internal series FET (green curve), and compared with the use of a 5 kΩ external series resistor and an unprotected op amp (red curve).


    Figure 3. Input current limit capability


    Figure 3 shows the ADA4096-2 in a unity gain buffer configuration, where the power supply is connected to GND (or ±15 V) and the positive input is scanned until the input exceeds the power supply by 32 V. Generally speaking, the input current is limited to 1 mA during positive overvoltage conditions and 200 µA during negative undervoltage conditions. For example, under a 20 V overvoltage condition, the ADA4096-2 input current is limited to 1 mA, thereby providing a current limit equivalent to a 20 kΩ resistor in series. Figure 3 also shows that the current limit circuit is effective regardless of whether the amplifier is powered or not.
    Please note that Figure 3 only represents input protection under abnormal conditions. Refer to Table 2 to Table 4 of the ADA4096-2 data sheet for the correct amplifier operating input voltage range (IVR).
    The AD7920 is a 12-bit, high-speed, low-power successive approximation ADC. It is powered by a single power supply from 2.35 V to 5.25 V and has a throughput of up to 250 kSPS. The device has a built-in low-noise, wide-bandwidth track-and-hold amplifier that can handle input frequencies above 13 MHz.
    The conversion process and the data acquisition process are controlled by CS and the serial clock SCLK, which creates conditions for the device to interface with the microprocessor or DSP. The input signal is sampled on the falling edge of CS, and the conversion is also started here. The device has no pipeline delay.
    AD7920 uses advanced design techniques to achieve extremely low power consumption under the following high throughput rates. To enter the shutdown mode, it must be at any time after the second falling edge of SCLK and before the 10th falling edge Change CS to high to interrupt the conversion process. Once CS becomes high within this window of SCLK, the device enters shutdown mode, the conversion initiated by the falling edge of CS is terminated, and SDATA returns to tri-state. If CS goes high before the second SCLK falling edge, the device will still be in normal mode and will not shut down. This can avoid accidental shutdown caused by glitches on the CS line.
    To exit this mode of operation and power up the AD7920 again, a pseudo conversion is required. At the falling edge of CS, the device starts to power up and continues to power up as long as CS is low until after the 10th falling edge of SCLK. After 16 SCLKs, the device is fully powered up, and the down conversion will generate valid data.
    If CS goes high before the 10th SCLK falling edge, the AD7920 returns to shutdown mode again. This can avoid accidental power-on caused by glitches on the CS line, or accidental bursts of 8 SCLK cycles when CS is at a low level. Although the device can be powered on on the falling edge of CS, it will be turned off again on the rising edge of CS as long as it does not exceed the 10th SCLK falling edge.
    Refer to the AD7920 data sheet for details on timing.
    Test Results
    An important indicator to measure the performance of this circuit is the amount of noise in the final output voltage measurement result.
    Figure 4 shows the histogram of 10,000 measurement samples. This data was obtained using the CN-0241 evaluation board connected to the EVAL-SDP-CB1Z System Demonstration Platform (SDP-B) evaluation board. For setting details, refer to the "Circuit Evaluation and Test" section of this circuit note.
    The power supply is set to 3.0 V, the output of the LDO is not turned off, and 10,000 data samples are collected at a rate of 250 kSPS. Figure 4 shows the acquisition results. The peak-to-peak noise is approximately 2 LSB, which corresponds to approximately 0.3 LSB rms.


    Figure 4. Histogram of codewords for the first 10,000 samples before shutdown


    Then set the SD shutdown pin connected to the ADP3336 low in the software to turn off the LDO output. After about 1 minute, set the shutdown pin of ADP3336 high again, turn on the output again, and collect the same number of data samples. Figure 5 shows the collection results.


    Figure 5. Codeword histogram of 10,000 samples after shutdown


    The figure above shows that when the input is high, the output of the ADA4096-2 is not latched during the shutdown period.
    Common changes
    It has been verified that the circuit can work stably and has good accuracy. The board is also compatible with the system demonstration platform SDP-S control board EVAL-SDP-CS1Z).
    With a slight modification to the circuit shown in Figure 1, the current can be monitored for input supply voltages up to +30 V. The +V pin of the ADA4096-2 is not connected to the +5 V of the ADP3336, but is directly connected to the monitored input power supply. In this configuration, the ADA4096-2 directly uses the input power supply.
    Circuit evaluation and testing
    This circuit uses the EVAL-CN0241-SDPZ circuit board and the EVAL-SDP-CB1Z system demonstration platform SDP-B controller board. The two boards have a 120-pin butt connector, which can quickly complete the setup and evaluate the circuit performance. The EVAL-CN0241-SDPZ board contains the circuit to be evaluated, as described in this note. The SDP-B controller board is used with CN0241 evaluation software to obtain data from the EVAL-CN0241-SDPZ circuit board.
    Equipment requirements
    l Windows? XP, Windows Vista? (32-bit) or Windows? 7 (32-bit) PC with USB port
    l EVAL-CN0241-SDPZ circuit evaluation board
    l EVAL-SDP-CB1ZSDP-B controller board
    l CN0241 SDP evaluation software
    l Able to drive 6 V/1 A DC power supply
    l Able to drive 5 V/2.5 A DC power supply
    l 2 Ω/12 W load resistance
    start using
    Put the CN0241 evaluation software CD into the CD drive of the PC and load the evaluation software. Open "My Computer" and find the drive containing the evaluation software.
    Functional block diagram
    The circuit block diagram is shown in Figure 1 of this circuit note, and the circuit diagram is shown in the "EVAL-CN0241-SDPZ-SCH-RevA.pdf" file. This file is located in the CN0241 Design Support Package.
    Set up
    The 120-pin connector on the EVAL-CN0241-SDPZ circuit board is connected to the connector marked "CON A" on the EVAL-SDP-CB1Z controller (SDP-B) board. Nylon hardware should be used to firmly fix the two boards through the holes at both ends of the 120-pin connector. In the case of power failure, connect a +6 V power supply to the pins marked "+6 V" and "GND" on the board. If you have a +6 V "wall power adapter", you can connect it to the tube connector on the board to replace the +6 V power supply. Connect the USB cable that comes with the SDP-B board to the USB port on the PC. Note: Do not connect the USB cable to the micro USB connector on the SDP-B board at this time.
    When you are ready to collect data, turn on the 5 V/2.5 A DC power supply. Adjust the voltage output accordingly to output the amount of current you want to measure.
    Figure 6 shows a screenshot of the CN0241 SDP evaluation software interface, and Figure 7 shows a screenshot of the EVAL-CN0241-SDPZ evaluation board. For information about the SDP-B board, please refer to the SDP-B User Guide.
    test
    Power on the +6 V power supply (or "wall power adapter") connected to the EVAL-CN0241-SDPZ circuit board. Start the evaluation software and connect the PC to the micro USB connector on the SDP-B board via a USB cable.
    Once USB communication is established, the SDP-B board can be used to send, receive, and capture serial data from the EVAL-CN0241-SDPZ board.
    When you are ready to collect data, turn on the 5 V/2.5 A DC power supply. Adjust the voltage output accordingly to output the amount of current you want to measure.
    Figure 6 shows a screenshot of the CN0241 SDP evaluation software interface, and Figure 7 shows a screenshot of the EVAL-CN0241-SDPZ evaluation board. For information about the SDP-B board, please refer to the SDP-B User Guide.


    Figure 6. CN0241 SDP evaluation software interface


    Figure 7. The EVAL-CN0241-SDPZ evaluation board connected to the SDP board


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