PXI Semiconductor Test System Solution Based on TS-900

Current status of the semiconductor testing industry

The electronics industry is under constant pressure to reduce its manufacturing costs. Time to market puts a lot of pressure on semiconductor manufacturers. In a short period of time after the new products are put on the market, profits are yes. Then, as competitors develop products with similar reserve prices, the profit level begins to decline. The development of an effective cost-saving test program is often a bottleneck hindering the introduction of new products into mass production.

For semiconductor suppliers, the cost of testing has always been regarded as a cost without "value-added". As shown in Figure 1, the cost of capital as a percentage of the average selling price (ASP) of ICs has gradually become smaller-from 5% in 2001 to approximately 1% in 2010. However, the ASP of the overall device is also decreasing, which means that in terms of cost, the cost of testing needs to be reduced at the same or greater rate as the reduction in device ASAP, which makes test engineers face greater pressure to find more cost-effective tests solution.

The actual situation is that increasing the utilization rate of traditional or "big" test systems by using techniques such as parallel testing (also called multipoint testing) will only produce limited improvements in test costs, but will not really solve the problem of test system costs. . For the testing needs of development laboratories, failure analysis laboratories or small batch production, the multi-site testing strategy will not improve the economics of testing.

Today's semiconductor devices include various digital, memory, analog, mixed-signal and RF modules, all of which are integrated in a single package or SoC (system on chip). As a result, the test solution must not only be cost-effective, but also must be flexible in order to address the test requirements of a range of circuit types including logic, memory, analog, MEM, and RF modules. The test solution must be able to provide engineers with cost-effective automated design verification, failure analysis and pre-production test activities without the need to use expensive "big".

The challenge facing today's test engineers is to create new test methods and systems that can significantly reduce test costs and solve the needs of configurable and flexible test solutions. Based on the development of (Compact PCI Extensions for Instrumentation) digital, analog and RF test products and systems, test engineers can use the platform to meet the test requirements of a series of ATE equipment. In particular, digital products provide a parameter measurement unit (PMU) function per pin, and now provide ATE semiconductor test functions with high value and performance. In addition, the PXI test system provides test engineers with a cost-effective ATE that can be used for failure analysis, prototype device verification and trial/early production runs-allowing "big iron" ATE to focus on mass production test applications while being compact and configurable Provide engineering test function in the platform.

Semiconductor test requirements

The basic test requirements of digital and mixed-signal devices include DC parameter test and functional test. For DC testing, the pins of the device must be characterized and a PMU (parameter measurement unit) is required. If a single PMU is used, the pins of all devices that can be accessed through multiplexing switches are required to achieve excitation voltage/measurement current or excitation current/measurement voltage. Once the DC parameter test is completed, the functional test of the device can be performed. In this case, a digitizer with deep enough memory, programmability per channel (voltage, load, and direction) and real-time comparison becomes the key to performing functional tests. The basic configuration to solve these functions is shown in Figure 2.

PXI Semiconductor Test System Solution Based on TS-900
The combination of a single PMU, switch network (multiplexing) and digitizer as shown in Figure 2 quickly becomes bulky and performance-limited for medium to high pin count devices. In addition, the combination of switching time and programming/measurement time for DC testing can easily take 10 or even 100 milliseconds, and the time for DC parameter testing will become very long.

A better solution and ATE or "big iron" systems usually use a PMU per pin or channel, which provides superior test performance (including speed and measurement accuracy). Figure 3 details the architecture of the digital instrument of the PMU configured per pin.

PXI Semiconductor Test System Solution Based on TS-900
Today, the GX5295 of Marvintest’s semiconductor test solution has 32-channel digital I/O and a per-pin PMU architecture, which can be used as a part of a compact PXI test platform, such as the TS-900 semiconductor test system-providing users with multiple channels of digital and The mixed-signal test system also has a small and compact PXI chassis footprint.

DC parameter test

As mentioned earlier, the PMU can use one of two modes to perform DC characteristic tests on the input and output lines of digital devices:

§ Forced voltage/measured current

Using this method, the PMU applies a constant voltage and uses its on-board measurement capability to measure the current drawn by the device/pin under test. It can also measure the voltage provided by the PMU.

§ Force current/measure voltage

Using this method, the PMU forces a constant current to flow through the device or draws a constant current from the device pins, and then measures the voltage. You can also measure the sink/source current of the PMU.

By combining the PMU and digital test functions of each channel in one instrument, a series of DC tests performed on digital and mixed-signal devices can be significantly simplified. Common DC tests performed on semiconductor devices include:

n VIH: (High level input) A positive voltage applied to the input of the device, the device will be accepted by logic high

n VIL: (low level input) the positive voltage applied to the input of the device, the device will be accepted by logic low

n VOL: (Low level output) The positive voltage output by the device is defined as the "guaranteed" low positive level under the specified load current

n VOH: (High level output) The positive voltage output by the device is defined as the "guaranteed" high positive level under the specified load current

n IIL: (Low level input leakage current) The input leakage current measured when the input is logic low level

n IIH: (High level input leakage current) Input leakage current measured when the input is logic high level

n IOS(H): (High-level short-circuit output current) The short-circuit output current when the output is logic high

n IOS(L): (low-level short-circuit output current) the short-circuit output current when the output is in a logic low state

Example: VOH, VOL and IOS test

The output voltage level test is used to verify the operation of the digital output when used under specified load conditions. They can also be used to simulate load conditions under poor conditions to observe the operation of the DUT when the output load exceeds its specified pole (for example, when it is short-circuited to ground). When performing these types of tests, a test current range that will not damage the device under test (DUT) should be selected to fully test the output.

The following example shows how to perform a VOH test on the digital output. The purpose of this test is to ensure that the DUT maintains an output voltage higher than its specified output high level while providing its rated drive current. For this test, the PMU is programmed to draw current from the DUT, simulating load conditions. Figure 5 shows the connection between the DUT and the digital instrument.

PXI Semiconductor Test System Solution Based on TS-900
To perform this test, the DUT is powered on, and one channel of the instrument (Ch1 in this example) is used to apply an input logic level that forces the output of the DUT to logic high. Please note that each instrument channel can be configured as PMU or digital I/O mode, providing the required flexibility and functionality to support VOH, VOL and IOS tests, which require that the output of the device be programmed to be correct before performing PMU measurements status.

The second digital channel (Ch2 in this example) is set to PMU forced current/measured voltage mode, and the initial current sink value will not damage the DUT output pin. Then, the PMU is programmed to change the device current from to the test value. Under each test current value, measure the output voltage of the DUT to ensure that it is within the specified voltage range of the logic high level. It can also measure the actual PMU test current and use it to provide a load and output voltage level curve for each (see Figure 6). In this case, the device under test (DUT) is an octal latch, and each output is tested for output level and current load.

PXI Semiconductor Test System Solution Based on TS-900
The above test techniques can also be used for VOL and IOS tests. For the VOL test, the output of the DUT will be programmed to a logic low level, and the output will be applied to the specified load of the output when measuring the output voltage level to ensure that it is within the device's specifications. For IOS parameters, the output will be programmed to the specified logic state, applied to the output short circuit and the measured result current.

Example: Leakage current test (IIL, IIH) and V-I test

The input of the test device includes the leakage current test and the protection diodes on each input terminal of the DUT. These tests are performed by gradually applying a constant voltage to the DUT input pins and measuring the input current at each step (Figure 7). Since the leakage current is usually in the uA range, the PMU should be set to a more sensitive current range to achieve more accurate measurements.

PXI Semiconductor Test System Solution Based on TS-900
To perform a leakage current test, the DUT will be energized and the PMU pin will be set to forced voltage/measure current mode. At each input voltage setting, the PMU measures the current drawn by the input and then verifies the value according to the DUT specifications. It is also possible to measure the actual test voltage being collected by the PMU. The testing techniques shown here can also be used for VIL and VIH testing.

Used to measure/characterize the input protection diode pins connected to the device and ground and VCC, the PMU is configured to force voltage/measure current, where the voltage is stepped in small increments to generate the V-I curve for each diode. Figure 8 shows the V-I curve of the protection diode of a TTL digital device. Note that the device begins to conduct at a junction voltage of approximately 0.4 volts.

PXI Semiconductor Test System Solution Based on TS-900
Semiconductor test automation

Today's test engineers are under constant pressure to shorten test development time and become more efficient in creating test programs. The test development framework is combined with software tools that can automatically create and execute device tests to provide test engineers with a powerful software development environment to improve test development and deployment productivity. For example, the TS-900 of the Marvin test solution includes ATEasy-a full-featured test execution environment for managing program development and deployment, and a test library that simplifies the creation and execution of standard tests. It provides IV characteristic curves for drawing And an interactive tool that supports two-dimensional Shmoo diagrams.

DC parameter automatic test creation

The ICEasy library includes a complete set of test functions to characterize the input and output DC characteristics of the device. Using the TS-900's per-pin PMU function, users can quickly create test programs for the following types of tests:

§ Openand Shorts

§ Input Leakage (IIL, IIH)

§ Input Voltage Threshold (VIH, VIL)

§ Output Short Circuit (IOSH, IOSL)

§ Output Voltage Threshold (VOH, VOL)

§ Power Consumption (IDD, IDDQ)

These pre-configured tests combine ICEasy's device pin and pin group mapping functions to provide users with a simple and simplified method to assign specific device pins and specify the pass/fail limits for each test. , Without the need to perform low-level instrument settings and controls. The result is faster test creation and shorter test times.

I-V Curve Tool

ICEasy's current-voltage (I-V) curve tool enables users to graphically plot the I-V characteristics of the device's ESD diode. This test method can gain insight into the device failure mechanisms that may affect the device's I/O pins, such as electrical stress (EOS), electrostatic discharge (ESD), bonding wire issues, and packaging issues. And recently, using I-V graphs as "impedance characteristics" may help to identify counterfeit products, where the impedance of known real parts or I-V labels are compared with suspicious parts.

ICEasy's I-V curve tool allows users to easily set the voltage and current ranges, step increments, and define specific pins (or pins) to be tested by name. In addition, all I/O pins can be drawn on the same graph, providing a simple way to compare the I-V curves of all devices. (See Figure 9) The drawing data can also be easily exported through the test execution environment (ATEasy) of TS-900. The ability to easily measure I-V characteristics and plot the results is a key feature for failure analysis and design verification applications.

Shmoo Plot Tool

ICEasy's Shmoo drawing tool allows users to easily change test parameters on the X and Y axes without programming-allowing test engineers to visually observe the pass/fail operating range of the device under test. The Shmoo drawing function of TS-900 is a recognized test method for equipment characterization and qualification, providing users with powerful design verification and early production test qualification technology. ICEasy's Shmoo tool supports automated and interactive control, allowing users to instantly change parameters or control the test and record the generated data through the TS-900 Test Manager (ATEasy). As shown in Figure 10, the Shmoo tool allows users to easily change the range of test parameters, such as VCC, clock frequency, edge placement, input level, etc., in order to fully characterize the pass/fail operating conditions of the device.

PXI Semiconductor Test System

Considering the availability of instruments and software to solve semiconductor test needs, test engineers can now choose to adopt the PXI architecture to meet current and future ATE requirements. Systems such as TS-900 provide comparable functions and performance for proprietary ATE systems. Today, 16 32-channel GX5295 digital I/O (PMU per pin) compact 20-slot PXI chassis can be used today Supports up to 512 digital I/O channels.

In addition, through standardization on the PXI platform, users can expand the system by combining various instruments including SMU, digitizer, AWG, and RF signal source and analyzer.

TS-900 has an integrated high-performance modular receiver interface, which is an ideal platform for users who wish to optimize the overall test strategy of the product life cycle. As shown in Table 1, compared with manual or semi-automatic benchtop test configuration, TS-900 is a new product
Products have significant advantages. Using test systems such as TS-900 can provide engineers with a faster and more automated process for characterizing devices, thereby shortening device characterization and verification from weeks to days. In addition, TS-900 can effectively solve the test cost of early production equipment without expensive capital cost (test time), fixed and long test development time, and does not rely on "big iron" ATE. With a wide range of software tools and intuitive software development/test execution environment (ATEasy), TS-900 meets the needs of the test platform and can bridge the test gap between engineering laboratories and mass production testing.