Make sure to pass some test tips and techniques of USB 3.0

Although there are early products on the market, the large-scale conversion to SuperSpeed USB has not yet begun. Part of the problem is that USB 2.0 has become very popular and the production cost is very low. High-bandwidth devices (such as video cameras and storage devices) have become batch applications of SuperSpeed USB. However, at least so far, cost factors restrict the implementation of USB 3.0 to higher-end products.

In addition to the inherent challenges of widespread deployment of any new industry standard, USB 3.0 is more than just a regular upgrade of USB 2.0, because USB 3.0 can provide a 10-fold increase in performance. Although performance has improved, consumers' expectations for low-cost interconnects have not changed. This puts tremendous pressure on engineers who can only use channels with much lower speeds while still ensuring reliability, interoperability, and high performance under various conditions. Testing to ensure physical layer (PHY) conformance has never been so critical or important.

USB 3.0 shares many other (such as PCI Express and Serial ATA) features: 8b/10b encoding, significant channel attenuation, and spread spectrum clocking. This article will discuss conformance testing methods and how to implement repeatable measurements on the sender, receiver, cables and interconnections. After mastering these skills, the journey to the SuperSpeed Platform Integration Laboratory (PIL) may be more exciting.

High Speed Vs. Overspeed

USB 3.0 can meet the increasing demand for bandwidth and can support applications to provide a more real-time experience. The number of USB devices currently in use is estimated to exceed 1 billion, so USB 3.0 needs to have backward compatibility to support traditional USB 2.0 devices. Of course, there are several important PHY differences between USB 2.0 and 3.0 (Table 1).



In order to meet the new challenges associated with higher speed interfaces, the SuperSpeed USB conformance test has been greatly modified. The verification of the USB 2.0 receiver includes a sensitivity test on the receiver. USB 2.0 devices must respond to test packets of 150mV or above, while ignoring (suppressing) signals below 100mV.

On the other hand, the SuperSpeed USB receiver must be able to work normally with many signal impairments, so the test requirements are more stringent than USB 2.0. Designers must also consider transmission line effects and use equalization techniques including de-emphasis at the transmitting end and continuous-time linear equalization (CTLE) at the receiving end. Nowadays, jitter tolerance testing is also required on the receiving side, but the use of spread spectrum clocks (SSC) and asynchronous reference clocks may cause interoperability issues.

Another important part of evaluating USB 3.0 serial data links is the complex interaction between measurement waveforms and interconnect channel behavior. The following assumption is no longer true: because the output signal at the transmitter conforms to the eye pattern template, the design can work normally when all channels reach a given loss condition. In order to understand the margin at the sending end under a given poor channel condition, in addition to the consistency requirement, you also need to model the combination of channel and cable, and use channel modeling software to analyze the channel effect (Figure 1).



Conformance test on the sender

The transmitter test needs to use various test patterns (Table 2). The selection of each pattern is based on the characteristics related to the test of the evaluation pattern. CP0 is a D0.0 scrambling code sequence used to measure deterministic jitter (Dj), such as data associated jitter (DDJ). CP1 is a D10.2 full-speed clock pattern with no scrambling code and does not generate DDJ, so it is more suitable for evaluating random jitter (RJ).



Jitter and eye height are measured with 1 million continuous unit intervals after applying equalizer functions and appropriate clock recovery settings (second-order phase-locked loop or PLL, closed-loop bandwidth is 10MHz, and damping coefficient is 0.707). The calculation method of the jitter result is to extract the jitter performance from the total measurement data with a bit error rate (BER) of 1 x 10-12. For example, using jitter extrapolation, the target RJ is equal to the measured RJ (rms) multiplied by 14.069.



Figure 2 shows a standardized transmitter-end conformance test device, including reference test channels and cables. Test point 2 (TP2) is close to the device under test (DUT), and test point 1 (TP1) is the remote measurement point. All normalized measurements at the transmitting end are performed on the signal at the TP point.

After the signal is collected at TP1, a software tool called SigTest can be used for data processing, similar to a formal PCI Express compliance test. For applications that require pre-compliance testing, characterization, or debugging, other tools can also be used to in-depth observation of design behavior under different conditions or parameters. A high-speed oscilloscope with USB 3.0 specific software can provide automatic standardization and information-based PHY transmitter testing. These tools can ensure that the test equipment is properly configured, thereby effectively saving time.

After the test is complete, a detailed pass/fail test will highlight possible design issues. If there is a conflict between different test locations (such as company laboratory, test room), the test should be executed again using the data saved during the previous test run.

Where further analysis is required, jitter analysis and eye diagram analysis software can be used for error checking and design characterization. For example, multiple eye diagrams can be displayed, allowing engineers to analyze different clock recovery techniques or analyze the effects of software channel models. In addition, different filters can be used to analyze the SSC effect and ultimately solve the system interoperability problem.

Balance considerations

Due to the large channel attenuation, SuperSpeed USB requires some form of compensation mechanism to open the eye diagram at the receiving end. The sender generally adopts equalization technology in the form of de-emphasis. The normalized de-emphasis ratio is specified as 3.5dB or 1.5x on a linear scale. For example, when the transition edge bit level is 150mVp-p, the non-jump edge bit level will be 100mVp-p.

CTLE consistent equalization implementations include active receiver equalization or passive high-frequency filters (such as those used in cable equalizers) on the die. This model is very suitable for conformance testing because it is very simple to describe the transfer function. The CTLE implementation has a set of poles and zeros in the frequency domain, so there will be a peak at the target frequency.

CTLE implementation is simpler for design and consumes lower power than alternative technologies. However, in some cases, they may not be enough due to limitations in adaptability, accuracy, and noise amplification. Other techniques include feedforward equalization (FFE) and decision feedback equalization (DFE), which use scale factor-weighted data samples to compensate for channel loss.

Both CTLE and FFE are linear equalizers, so the signal-to-noise ratio deteriorates due to the increase of high-frequency noise. However, DFE uses nonlinear components in the feedback loop, which can minimize noise amplification and compensate for inter-symbol interference (ISI). The example shown in Figure 3 shows a 5Gbit/s signal after significant channel attenuation and a signal equalized using de-emphasis, CTLE and DFE techniques.



USB 3.0 receiver test

The USB 3.0 receiver test is similar to the consistency test of other high-speed serial bus receivers. It is generally divided into three stages. The first is the pressure eye diagram calibration, and then the jitter tolerance test is the analysis. Let us look at the flow chart of this process (Figure 4).



Stressed eye calibration uses a bad signal, which is usually impaired in both the vertical direction (through increased jitter) and the horizontal direction (by setting the amplitude to the value that the receiving end can see when deployed). When any test fixture, cable, or instrument is changed, a pressure eye calibration must be performed.

The jitter tolerance test uses a calibrated stressed eye diagram as input, and then applies additional sinusoidal jitter (SJ) at higher frequencies. This kind of SJ will act on the clock recovery circuit in the receiving end, so not only the receiving end is tested with the difference signal condition, but the clock recovery has also been clearly tested. , After the completion of the analysis and evaluation of the test, whether additional design tasks need to be performed to achieve consistency.

The pressure eye diagram calibration process first needs to set up the test equipment with conformance fixtures, cables and channels (Figure 5). The next step is to repeatedly measure and adjust various types of applied stress, such as jitter. The DUT is not needed when the calibration step is performed, but the compliance test fixture, channel, and specific data pattern generated by the test equipment are required. The test instrument should be able to perform two functions-pattern generation functions that can increase various stresses, and signal analysis functions such as jitter and eye diagram measurement.



Three kinds of damage calibrations must be completed when calibrating the pressure eye diagram: RJ, SJ and eye diagram height. Each type of calibration requires specific settings for the pattern generator and analyzer. The compressed eye diagram must also be calibrated for each set of cables, adapters and instruments.

Due to the use of different adapters and reference channel groups, the host and the device will go through different pressure eye diagram calibration procedures. Once completed, the settings for calibrating the eye diagram can be reused, and recalibration is only necessary when the device settings are changed.

Additional pattern generator requirements

All the items required for calibration have already been introduced, let us look at the additional requirements for the pattern generator for each step of calibration, including the data pattern used, the degree of de-emphasis, and whether the SSC should be activated or not. In the pressure eye diagram calibration scheme, two patterns are listed, namely CP0 and CP1. Table 3 lists all USB 3.0 conformance patterns for reference.



CP0 is a 8b/10b code, PRBS-16 data pattern (the result of sending D0.0 characters to the USB 3.0 transmitter for scrambling and encoding). After 8b/10b encoding, the length of long consecutive 1s or consecutive 0s is reduced from 16 bits in the PRBS-16 pattern to 5 bits. CP3 is similar to the 8b/10b coded PRBS-16 pattern, which contains short (single bit) and long identical bit sequences.

CP1 is the clock pattern used for RJ calibration. Many instruments use dual-Dirac random and deterministic jitter separation method in RJ measurement. Using clock patterns can avoid some of the drawbacks of the dual-Dirac method, such as changing DDJ to RJ, especially for long patterns. By using the clock pattern, the DDJ as a result of the ISI will be eliminated from the jitter measurement, resulting in a better RJ measurement result.

The lossy channel between the pattern generator and the analyzer (ie, the USB 3.0 reference channel and cable) will cause frequency-dependent losses that appear as closed eyes in the vertical and horizontal directions (Figure 6). In order to solve this loss problem, it is necessary to use the transmitter de-emphasis technology to enhance the high-frequency components in the signal, so that the working link with a BER of 10-12 or higher has a sufficiently good receiving eye pattern.



It can be seen from these eye diagrams that all amplitudes are nominally the same without de-emphasis. After using de-emphasis, the amplitude of the transition edge bit is higher than the amplitude of the non-jump edge bit, thereby effectively enhancing the high-frequency component of the signal.

After passing through the lossy channel and cable, the signal without de-emphasis will be affected by inter-symbol interference (ISI), and the eye opening will be smaller than the signal after de-emphasis. At the same time, the signal using de-emphasis is fully open. It can be seen from this that the degree of de-emphasis will affect the degree of ISI and DDJ, which in turn affects the eye opening of the receiving end.

SSC is often used in synchronous digital systems (including USB 3.0)

Reduce electromagnetic interference (EMI). If SSC is not used, the carrier frequency (ie, 5Gbps) and its harmonics in the digital stream spectrum will have large spikes, and may exceed the adjustment limit (Figure 7).



To prevent this problem, SSC can be used to spread spectrum energy. In this, the carrier frequency is modulated by a triangular wave. The frequency "spread" amount used for the receiving end test is 5000ppm or 25MHz, and the frequency modulation period is 33kHz or every 30μs, which is a cycle of the triangle wave. After SSC, the energy in the frequency spectrum has been expanded, and no single frequency will break the specification limit.

As mentioned earlier, the receive-side equalization in USB 3.0 can improve signals damaged by inter-symbol interference, which is caused by frequency-related losses in the reference channel and the cable. This concept is equivalent to de-emphasis—the high-frequency components in the signal are boosted by signal processing methods.

Although the receiver equalization circuit in the device or host is related to the specific implementation, the USB 3.0 standard specifies CTLE for conformance testing (Figure 8). This kind of CTLE must be implemented by a reference receiver such as a bit error rate tester (BERT) or an oscilloscope before the conformance test measurement (all for the transmitter test, in this case, the receiver pressure eye diagram calibration), And usually adopt the way of software simulation.



Using CTLE simulation for jitter measurement mainly affects the jitter caused by the signal processing method, that is, ISI. CTLE simulation does not affect jitter components that are not related to data patterns (such as RJ and SJ), although CTLE is required for both measurements according to the Conformance Test Specification (CTS). On the other hand, the eye height will be directly affected because ISI affects the measurement.

The clock recovery "golden PLL" with consistent jitter transfer function (JTF) must be used for jitter measurement, as shown by the blue line in Figure 9. JTF indicates how much jitter is transferred from the input signal to the downstream analyzer. In this example, the -3dB cutoff frequency is 4.9MHz.



At lower SJ frequencies (along the slope of the JTF, where the PLL loop response is flat), the recovered clock tracks the jitter on the data signal. In this way, the data jitter relative to the clock will be attenuated according to JFT. At higher SJ frequency points, the JTF flattens, the PLL response slopes downward, and the SJ part of the signal is transferred to the downstream analyzer. With the exception of the SJ during the compression eye diagram calibration, all measurements require the use of a consistent JTF.

Once the stressed eye is calibrated, the receiver test can begin. USB 3.0 is different from the previous USB 2.0 and requires a BER test. The BER test in the form of jitter tolerance test is only a test item required by the receiver test. The jitter tolerance test uses the differential input signal condition to test the receiving end (see the previous section for the calibration of the stressed eye diagram). At the top of the stressed eye diagram, a series of SJ frequencies and amplitudes around the -3dB cutoff frequency of the JTF and covering a certain frequency range are injected into the test signal. At the same time, the error detector monitors the error or bit error at the receiving end and calculates the BER.

Summary of this article

As USB 3.0 begins to move toward the mainstream, it is necessary to carry out successful conformance and testing on the sender and receiver, which is the key to bringing new products to the market. These products are not only required to work with other USB 3.0 devices, but also to meet consumer expectations for performance and reliability under various conditions.

The dramatic improvement in performance has brought many new test requirements, and has also made the design and comparison of the previous generation standard
Quasi more challenging. Fortunately, there is a whole set of testing tools and resources that can be used to assist with the SuperSpeed USB trademark.