Principle and hardware design scheme of high-speed arbitrary waveform generator

The application of the waveform generator can be seen everywhere in life, among which the most used waveform generator is the arbitrary waveform generator. In order to enhance everyone's understanding of the waveform generator, this article brings a design example of a high-speed arbitrary waveform generator. If you are interested in the content of this article, you might as well read it patiently.
Arbitrary Waveform Generator is one of the fast-developing products among electronic measuring instruments. It can output standard function signals as well as non-standard function waveform (arbitrary waveform) signals defined by the user, and has a wealth of analog modulation (AM, FM, PM) and digital modulation (FSK, PSK) functions. Different application fields provide various standard or non-standard signals, especially in the development, production, and maintenance of underwater sonar, communications, radar navigation, electronic countermeasures and other equipment. It is an indispensable signal generator. Based on digital frequency synthesis technology, a design scheme of high-speed arbitrary waveform generator is given.
1 Hardware design of high-speed arbitrary waveform generator
1.1 The working principle of arbitrary waveform generator
There are currently two schemes for the generation of arbitrary waveform generators. One scheme is to use direct digital frequency synthesis (DDS) technology to generate arbitrary waveforms. The working principle is shown in Figure 1.



A standard DDS circuit should be composed of the following parts, including phase accumulator, waveform memory, D/A converter, low-pass or band-pass filter. Arbitrary waveform data is written into the waveform memory through the man-machine interface in advance, and the function of the phase accumulator is to sample the clock phase output by the reference oscillator according to the input frequency control word. When the step size of the phase accumulator is K. In the output frequency formula of arbitrary waveforms, Fs is the fixed sampling clock frequency, and n is the length of the phase accumulator. Changing the frequency control word K can change the output frequency of the DDS.
The arbitrary waveform generator composed of DDS technology has the advantages of high output frequency resolution and continuous frequency change phase, but it also has two important defects. The first is that when the phase increment of the phase accumulator is large, the output waveform will produce jitter; secondly, because the DDS technology does not read the data in the waveform memory point by point, the output waveform will lose a lot of useful information.

Another design scheme of the arbitrary waveform generator is shown in Figure 2. Its working principle is that the clock of the arbitrary waveform generator changes the output address of the address generating circuit composed of the counter by adding 1 to the counter, and the counter sequentially sweeps the waveform memory Each address in each address until the end of the waveform data, the waveform data in each address is sent to the D/A converter to convert the digital signal into an analog signal, and then the output signal of the D/A converter needs to pass a low The pass filter smoothes the transition edge of the output signal of the D/A converter to obtain the desired arbitrary waveform. In this scheme, all the waveform data is sent to the D/A converter, so the waveform data will not be lost, but all the waveform data content defined in the waveform memory is output, and the output signal frequency of the arbitrary waveform is variable. Then the frequency of the sampling clock must be variable, which is clearly different from the arbitrary waveform generator composed of DDS. In the output frequency formula of the arbitrary waveform using this scheme, Fs is the variable sampling clock frequency.
Using this scheme, the circuit structure is simple and can output complex arbitrary waveforms, which is suitable for high-speed arbitrary waveform generators. The sampling rate of the arbitrary waveform generator based on this scheme can reach 200 million times per second, and the output frequency of the arbitrary waveform can reach 50 MHz. The block diagram of the overall circuit of the high-speed arbitrary waveform generator waveform is shown in Figure 3.
The principle and hardware design scheme of high-speed arbitrary waveform generator
1.2 Design of arbitrary waveform generating circuit
As shown in Figure 4, a complete arbitrary waveform generating circuit is mainly composed of a clock generating circuit, an address counter, a waveform memory, a latch, a parity data selection circuit and a D/A converter.

    The clock generation circuit is used to generate the variable clock required by the arbitrary waveform generator. It can usually be composed of a phase-locked loop circuit controlled by a single-chip microcomputer. In the actual design, a phase-locked loop integrated circuit is used to generate a clock signal with a frequency of 100 MHz. The output signal of the circuit is sent to the clock input of the address counter to drive the address counter to scan the data in the waveform memory. The address counter uses a 15-bit binary synchronous counter, which is logically equivalent to the 4-chip 74F161 cascade, and the 15-bit address output by the address counter The data is connected to the address input of the waveform memory. The waveform memory uses four pieces of 32 K×8 (read and write speed of 12 ns) SRAM cascaded to form a 32 K×32 SRAM array. Among the 32-bit data at the output of the SRAM array, 24 Bits are waveform data, 2 bits are control signals, and the remaining 6-bit data lines are not used. The resolution of each waveform point is 12 bits, and each address stores the data of two waveform points. The arbitrary waveform signal of a single segment can be up to 64 K points. The two control signals are stop bit, sync bit, and stop bit data line. The D flip-flop is connected to the preset number control terminal of the address counter. When scanning to a waveform address is detected, the stop bit sets the preset number control terminal of the address counter, so that when the next clock comes, the address counter will again Address from the first address of the arbitrary waveform to read the waveform data. The synchronization bit in the control signal is used to output an external synchronization signal. The 24-bit arbitrary waveform data output by the waveform memory is latched by the latch and sent to the input end of the 12-bit parity data selection circuit. As mentioned above, each address of the waveform memory stores the waveform data of two points. When the waveform data is written to the waveform memory through the human-machine interface, the waveform data of one point is composed of the odd-numbered data in each address. The data of one point is composed of even-numbered bits. The advantage of this is that when each sampling clock comes, the data of 2 waveform points can be read at the same time, so that the frequency of the output waveform is doubled, which is equivalent to the frequency of the sampling clock. It has doubled, greatly improving the performance of the instrument. The 12-bit parity data selection circuit is logically equivalent to three 74F157. The output terminal of the parity data selection circuit is connected to the input terminal of the D/A converter. The function of the D/A converter is to convert the digital signal read from the waveform memory into an analog signal. Since the clock frequency is 100 MHz, D/A converter The /A converter selects the AD975 with a rate of 125 million times per second. According to the sampling law, the fundamental frequency of the output signal will be lower than half of the reference clock frequency used. In this scheme, the sampling clock frequency is 100 MHz. An arbitrary waveform can be composed of at least 4 points, and two are read in each clock cycle. Waveform data, so the frequency of the output arbitrary waveform signal is 50 MHz. In the above circuit, 15-bit synchronous binary address counter, 24-bit latch, 12-bit parity data selection circuit and related control circuit can also be implemented by high-speed CPLD.
1.3 Filter design
The signal after D/A conversion usually contains more clock components and steeper transition edges. In order to reduce the jitter of the output waveform and suppress higher harmonics, it is necessary to select an effective filter in the design of the arbitrary waveform generator. It is very important. The high-speed arbitrary waveform generator can output both sine waves, triangle waves, sawtooth waves, pulse waves and arbitrary waveforms. Therefore, filters with different performances should be selected according to different frequency bands and waveforms. Elliptic (EllipTIc) filtering The filter has steep transition characteristics and is suitable for use as an output filter for sine waves. Triangular waves, sawtooth waves and arbitrary waves have rich frequency spectra. Therefore, the filter is required to have good amplitude-frequency characteristics within the passband to ensure that the signal passes through the filter. After the filter, no distortion is generated, and spurious signals can be filtered out. The elliptic filter will produce violent ringing on other waveforms other than the sine wave, and the Gaussian filter with linear phase can meet these requirements. In this solution, the sampling clock of the arbitrary waveform generator is variable, so it is The cut-off frequency of the low-pass filter must also be changed, otherwise it will not have a filtering effect in some frequency bands, or useful signals in high frequency bands will be attenuated. For this reason, the cut-off frequencies of 25 MHz and 50 MHz are adopted in this design. The first-order elliptic filter and the 20 MHz Gaussian filter with a cut-off frequency are programmed and selected by the single-chip microcomputer according to different situations. Figure 5 shows the circuit of a seventh-order elliptic filter with a cut-off frequency of 50 MHz and a Gaussian filter with a cut-off frequency of 20 MHz.
The principle and hardware design scheme of high-speed arbitrary waveform generator
1.4 GPIB interface design
Although there are many new interface standards in intelligent instruments, such as USB, LAN, etc., the GPIB (General Purpose InteRFace Bus) interface is still recognized as a standard interface for intelligent instruments in the industry. In this solution, the GPIB interface is used from the PC to any The waveform generator data can be remotely controlled through the GPIB bus. The GPIB interface circuit is composed of NI's NAT7210 GPIB application-specific integrated circuit and TI's GPIB bus drivers SN75160 and SN75162. NAT7210 outputs standard GPIB Format data, in line with the IEEE488.2 standard, the role of the GPIB bus driver is to enhance the driving capability of the interface. Refer to the literature for the connection method between NAT7210 and SN75160, SN75161 and the one-chip computer.
2 Software design of high-speed arbitrary waveform generator
The software of the high-speed arbitrary waveform generator includes two parts: the waveform editing and software of the PC part and the microcontroller control software inside the instrument. The waveform editing and software have various arbitrary waveform editing capabilities, such as straight line editing, curve editing, and formula editing. , Modulation waveform editing mode. Waveform editing and software can communicate with the arbitrary waveform generator through the GPIB interface to complete the remote monitoring of arbitrary waveform data and the instrument. The single-chip microcomputer control software structure inside the instrument adopts the classic main program loop and interrupt service mode, and its flow chart is shown in Figure 6. After the instrument is powered on, it first performs self-check and software and hardware initialization, and then enters the loop of the main program. The loop of the main program is the process of waiting for interrupt processing. It judges the interrupt source according to the interrupt request, turns on the interrupt and turns to the corresponding interrupt processing Subroutine, complete the corresponding operation or hardware control.
The principle and hardware design scheme of high-speed arbitrary waveform generator
3 Concluding remarks
After testing the completed arbitrary waveform generator prototype, the arbitrary waveform generator adopting this scheme can output arbitrary waveforms as low as 10 MHz and as high as 50 MHz. The output waveform is stable and there is no loss of waveform data. Through the waveform editing on the PC The software can generate a variety of arbitrary waveforms, which can be widely used in various fields such as national defense, scientific research, education, and industrial production.