Mass memory integrated circuit testing

The test system of mass memory integrated circuits is a technology innovation fund project of small and medium-sized technology-based small and medium-sized enterprises. It is a test system researched and developed based on the development trend of mass memory integrated circuits SDRAM, DDR SDRAM and flash RAM. The main content of the plan is the research and development of test methods and test procedures, followed by the development of test boards, adapters and production test equipment, and equipment structure production and debugging. The characteristic is based on the structure of the large-capacity memory integrated circuit, the use of brand-new testing technology theory and more general testing equipment, to achieve laboratory testing and mass production chip testing and finished product testing. At present, the equipment that can test high-megabit memory circuits in large quantities is very expensive, and the low-cost dedicated memory circuit tester cannot meet the reliability and versatility requirements of the test. Therefore, the project will greatly improve the production capacity of domestic memory circuits and reduce Product cost, improve the availability of memory circuits, have significant economic and social benefits.
    1 Basic principles of the test system
    According to the technical characteristics of large-capacity memory circuits, regardless of EEPROM, DRAM, SDRAM, FLASRAM, etc., there are four different reading and writing methods: fast block (BANK), page (PAGE), single cell and continuous multiple cells. This system makes full use of different reading and writing methods for testing. First, the correctness of reading and writing of the storage unit is tested in a page mode, and then the accuracy of continuous writing of fixed data is tested in a block mode, and then multiple units are continuously written to change. The stability of the data, test the reliability of the data under the continuous cyclic changes of a single unit write, run 4 different test modules in this order, can analyze and test the various states of the memory circuit very accurately, and test the large-capacity memory circuit The test items of SDRAM and flash RAM and the testability of the storage unit are 100%, and the system timing accuracy is ±500 ps, which fully meets the product index requirements of SDRAM and flash. The technical problem of this project lies in the innovation of the test method of large-capacity memory integrated circuit and the development of corresponding test equipment. It has 5 key technical characteristics.
    1.1 Use vector technology "V2MTM" to test large-capacity memory
    Due to the continuous increase in memory circuit capacity and the enhancement of test simulation capabilities, the number of test vectors has greatly increased. It is impossible to use traditional small and medium test equipment. Even large-scale test equipment only seeks complex page-based solutions. Linear test, this is the main reason that the test time increases with the increase of capacity and the cost increases. The use of virtual vector memory test technology can provide up to 4096 test vectors to meet the test requirements of large-capacity memory circuits with a capacity of more than 100 megabytes and a data rate of sub-nanoseconds. The whole test process is based on vector technology, which realizes simultaneous multi-point and multi-circuit test, keeping the time and cost basically unchanged.
    If it is a 128M capacity memory circuit, the page capacity is 32K, then the circuit has 2048 pages. The test equipment will provide 2048 test vectors to achieve simultaneous testing of 2048 points, which greatly shortens the test time compared to linear tests.
    1.2 Adopting indexed scanning and rereading technology
    Scanning test technology is mainly designed for the problem that the memory circuit is more sensitive to the level. Scanning path: boundary access scan, page access scan, cell access scan, make full use of the structural characteristics of memory circuit row and column multiplexing, so that any pin of the memory can be used as a scan pin for testability, which improves testability And test accuracy.
    The memory circuit is more sensitive to the level and will give false test results. Assuming that A1 is internally open, A1 will be sensed as either a high level or a low level when reading and writing. If the induction is low, that is, A1=0, try to read and write any unit of 10. Since the internal open circuit induction of A1 is A1=O, it is actually only reading and writing to the unit of OO. On the surface, the reading and writing test results of unit 10 are correct. In fact, only the OO unit read and write test results are correct, and therefore give wrong results. This problem can be solved by index scanning and rereading technology. In order to increase the test speed, select 256B or larger capacity in the boundary area. Assuming that it corresponds to an 8-bit address, first write different data to units 00000000 to 11111111, such as writing 00H, 01H, 02H...255 respectively. When reading, AO, A2, A3, A4, A5, A6, A7 are fixed to 0, change the address of A1:
    If the addresses are reliable, 00000000 unit will write 00H, 00000010 unit will write 02H, when 00000000 unit is read DATA=https:///00H; A1 index is 1,00000010 when unit read DATA=02H
    For example, the internal open circuit induction of A1 is low, that is, A1=O, 00H is written to 00000000 unit, when writing 00000010 unit, because A1=O, 02H will write 00000000 unit to cover 00H. DATA=https:///02H when reading 00000000 unit, A1 index is 1,00000010 when reading DATA=02H, the data is the same, it can be judged that the index pin A1 is wrong. Each address is indexed one by one, and the testability and test accuracy of all indexed pins are determined by whether the data is the same when read.
    1.3 Real-time data analysis technology
    Through the logic analysis function, the system host can quickly isolate the error of the device under test and display the relevant data. It can also stop or save it on a specified vector in the event of a fault, perform logical statistical analysis, and display it quickly and accurately. The status of the storage unit is classified and displayed for the test circuit to improve the usability of the storage circuit.
    For large-capacity memory circuits, it is difficult to guarantee the correctness of the entire circuit. The entire circuit is often discarded due to the damage of a small number of units. In order to make full use of the circuit, the circuit can be classified into different levels. If it is a 128M capacity memory circuit, when the damaged unit is partially concentrated in the high half of the circuit, select the low half by pulling down the bit address, or when the damaged unit is concentrated in the low half of the circuit, select the high by pulling up the bit address. Half of it can be used as a 64M capacity memory circuit. By adjusting the address structure, it can continue to be subdivided into 32/1618/412 mega-capacity memory circuits for use.
    1.4 CHIP SET initialization technology and multi-CPU technology
    The design of the system's test control terminal adopts CHIP GROUP (chip combination) technology, which has a main CPU (upper computer) and multiple test CPUs (lower computers). The system software initializes the control terminal. According to the specific test of the memory circuit, Developed and designed a new BIOS system program, including designing the structure of the global variable descriptor GDT, the structure of the local variable descriptor IDT, the global variable descriptor table GDT-TABLE vector, the code segment CODE-DES vector, and the data segment DATA-DES vector , Storage select MEMORY-SEL vector, test segment TEST-DES vector, define global variable descriptor register GDT-R, local variable descriptor register IDT-R, etc. In this way, the BIOS of the control terminal is redesigned so that the terminal can directly test the memory to be tested. The test capacity is controlled by software, and there are many options for different chip sources and different capacities. When testing, only need to set the type, capacity, test start vector and end vector of the memory to be tested, so that the test system can perform self-defined test on the memory as required. Through the initialization of CHIPSET, various internal parameters, variables and vectors are defined, so that the main CPU only performs the management of each test CPU and the data logic analysis of the test results to meet the requirements of memory circuit testing.
    1.5 Test program modularization technology
    The system uses four different test program modules to test the memory circuit, and uses different read and write methods to test the accuracy and reliability of the memory unit.
    (1) Page-WR-RD read function module to test the correctness of reading and writing of the memory circuit.
    (2) FAST-WR-RD function module to test the accuracy of the memory circuit to continuously write fixed data.
    (3) MODIFY-WR-RD module, to test the accuracy of the memory circuit when continuously writing changing data.
    (4) MOVE-WR-RD function module to test the accuracy of the memory circuit in the fast writing of continuously changing data.
    The memory circuit test system uses a computer as the control terminal, adopts virtual vector technology, index scanning technology, real-time data analysis technology, CHIP SET technology and the initialization configuration of the design computer CHIP SET, timing control technology, development and testing of memory circuit application programs, and equipment Corresponding manipulator and probe station interface, realize the test of large-capacity memory circuit.
    2 Memory circuit test program
    Different functional modules of the system test the memory circuit in different ways to test various parameters of the storage unit, integrate the results of different test methods and all test vectors, and classify the accuracy and reliability of the storage unit , Output display. The memory circuit test program is part of the test system.
    2.1 Page-WR-RD module
    The FP-WR-RD module is to test the correctness of the memory circuit in PAGE (page) mode. This method is used to write and read data in a "WORD" 32bit/time mode. Each time data is written, all memory cells are not completely filled, but according to the characteristics of the memory circuit, the memory circuit is 64M bytes (in 8M bytes). ×8 as an example) The storage unit to be tested is divided into different areas (400I-King) in units of 64K bytes. It is more correct to read out after writing to the storage unit in units of 64K bytes. If there is an error, call the error recording subroutine. If there is no error, continue to write the next data. The data to be written is processed in the form of character strings, one data is fetched each time.
    2.2 FAST-WRITE-READ module
    The FAST-WRITE-READ module is to test the accuracy of the memory circuit continuously writing fixed data. It writes all the 16M bytes memory cells with the same data at 32bit/time, and then reads out all the data to test its accuracy. The purpose of this module is to test the accuracy of each memory cell in the fast continuous write/read operation mode of the memory circuit.
    2.3 MODIFY-WRITE-READ module
    The MODIFY-WRITE-READ module tests the accuracy of the memory circuit when continuously writing changed data. The variable content of each write data is inverted, and the content of every two consecutive writes is the opposite. If it is detected every two times when reading data If the content is not the other way around, there is an error in the storage unit. This function is used to detect whether the storage units interfere with each other and cause instability.
    2.4 MOVE-WRITE-READ module
    The MOVE-WRITE-READ module tests the accuracy of the memory circuit in fast writing continuous cyclic data. The content of the data variable EAX written each time is shifted to the left by one bit, and the data written in each adjacent time is different. Further check the stability of the storage unit.
    2.5 Results display output module
    The purpose of the memory circuit test is to classify and identify the memory circuit according to its error storage unit. The result of the identification must be easy to record, distinguish, weld and use to meet the needs of actual production, and the result data of the above module test is stored In EAX, the address is stored in ES: [DI], the memory circuit must be classified and identified, and the manipulator must be transported to the corresponding assigned card position.
    2.6 Display interface function module
    After the test system is turned on, a test interface should appear on the display screen, showing the test system configuration, the type of memory circuit being processed, and the operating mode being executed, so as to observe which mode the memory circuit is more sensitive to, and it is targeted during processing. Strengthen the test mode processing. Display the number of loops in the test run and observe the performance of the memory circuit under test in the working state, so as to observe the long-term stability of the memory circuit. The large-capacity memory circuit manufacturers have slightly different storage technologies. In the test interface, software technology is used to solve the adaptability problem in product transformation. As long as the relevant software variables are set, various memory circuits can be applied.
    3 Technical advantages
    The system uses the above-mentioned key technologies and unique test module methods to test various indicators (speed, accuracy, stability) of the memory circuit, and has independent intellectual property rights. As a special test equipment for memory circuits, the program design completely simulates the various states of the memory circuit in actual work. It has strong test ability, fast speed, high testability, adapt to various memory circuits, and has greater flexibility. Due to the use of virtual vector memory technology, this test system has considerable room for development in terms of test capacity, and the test cost is very low. It has certain advantages in the testing technology field of memory integrated circuits and the testing system market.