Timing compliance test solution

In the process of a certain product test, engineers reported that there were occasional data abnormalities. After systematic analysis, the Zhiyuan electronic test team speculated that there may be occasional abnormalities in the timing of the SPI communication bus of the ADC chip. However, because the probability of abnormal occurrence is very low, what should I do? How to locate the occasional timing problem of the SPI communication bus?
One, build a test environment
The SPI bus test point is located at the bottom of the main board of the host. The clock frequency is about 33MHz, which is a high-frequency signal. Therefore, the termination method of the probe is more particular; for the convenience of testing, as shown in Figure 1, the test point is led out with a short line. The ground wire is also drawn from the front-end self-winding wire, which can improve signal integrity and reduce the impact of oscilloscope sampling on the sequence analysis process.


Figure 1 Probe termination test point


2. Long-term monitoring and positioning abnormalities
The time sequence analysis software of ZDS4000 has a long-term statistical function. After get off work, the oscilloscope is set up, and the SPI bus timing of the data acquisition instrument is continuously monitored for one night. When the next day goes to work, the monitoring and analysis results are exported, as shown in Figure 2, one night A total of 72,185 measurements were taken, of which 1,347 were measurement failures. The reason for the abnormality was that the SPI data setup time did not meet the timing requirements of the subsequent chip. The oscilloscope automatically saved these 1347 failed tests and opened the 1345th test. As shown in Figure 3, it shows that the current setup time is 3.75ns (including screenshots of timing violations), which does not meet the 4ns setup time requirement of the subsequent chip. Moreover, the historically bad timing is 3.5ns and the timing is 8.5ns, and the problem can be located.


Figure 2 Time series analysis statistical results


Figure 3 Measurement result failure report

Three, locate the problem and do stability verification
Through the above test and analysis, the setup time of the SPI bus is too small and the hold time is too large. Adjusting the clock signal timing delay is about 6.5ns, and a better timing analysis can be obtained, that is, the data signal establishment time and the data signal retention time are as close as possible. After the rectification, the timing analysis software was used to measure the stability of the SPI bus overnight. The measurement results are shown in Figure 4. The timing analysis was performed 72,842 times. All the tests passed, and each measurement item was PASS. The setup time of the previous question item is 10.75ns and 13.5ns, which is perfect, which shows that the timing of the SPI bus is very stable.


Figure 4 Timing analysis measurement results


Timing consistency and stability analysis has always been a problem in the industry. The current timing conformance test program of ZLG Zhiyuan Electronics already supports I2C, SPI, I2S and MIPI-RFFE.